Intel E7-8891 v2 CM8063601377422 Manual De Usuario

144

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

Read Pending Queue Age Counters. 

At a high level, the goal of any page closing policy is to trade off some Premature Page 
Closes (PPCs) in order to avoid more Overdue Page Closes (OPCs). In other words, we 
want to avoid costly Page Misses and turn them into Page Empties at the expense of 
occasionally missing a Page Hit and instead getting a Page Empty. The scheme achieves 
this by tracking the number of PPCs and OPCs over a certain configurable window (of 
requests). It then compares the two values to configurable thresholds, and adjusts the 
amount of time before closing pages accordingly. 

31:12

RV

-

Reserved.

11:0

RW

0x0

MR0_SHADOW (mr0_shadow):

BIOS program this field for MR0 register A11:A0 for all DIMMs in this channel. 

iMC hardware is dynamically issuing MRS to MR0 to control the fast and slow 

exit PPD (MRS MR0 A12). Other address bits (A[11:0]) is defined by this 

register field. A15:A13 are always zero.

31:26

RV

-

Reserved.

25:16

RW

0x0

IOCount (iocount):

This is the RPQ Age Counter for the Medium and Low priority (VC0) 

nonisochronous transactions issued from HA. The counter is increased by 

one every time there's a CAS command sent. When the RPQ Age Counter is 

equal to this configured field value, the nonisochronous transaction is aged 

to the next priority level. When programming this field, BIOS must set this 

field to nonzero value before setting the MCMTR.NORMAL = 1.

15:0

RV

-

Reserved

31:29

RV

-

Reserved.