Intel E7-8891 v2 CM8063601377422 Manual De Usuario
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CM8063601377422
Processor Uncore Configuration Registers
182
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13.7.4.3
CAPID1
This register is a Capability Register used to expose enable/disable BIOS use.
Type:
CFG
PortID: N/A
Bus:
1
Device: 10
Function:
3
Offset:
0x88
Bit
Attr
Default
Description
31:31
RO_FW
0x0
DIS_MEM_MIRROR:
Disable memory channel mirroring mode. In the mirroring mode, the server
maintains two identical copies of all data in memory. The contents of branch 0
(containing channel 0/1) is duplicated in the DIMMs of branch 1 (containing
channel 2/3). In the event of an uncorrectable error in one of the copies, the
system can retrieve the mirrored copy of the data. The use of memory
mirroring means that only half of the installed memory is available to the
operating system.
30:30
RO_FW
0x0
DIS_MEM_LT_SUPPORT:
Disable Intel TXT support
29:26
RO_FW
0x0
DMFC:
This field controls which values may be written to the Memory Frequency Select
field 6:4 of the Clocking Configuration registers (MCHBAR Offset C00h). Any
attempt to write an unsupported value will be ignored.
[3:3] - If set, over-clocking is supported and bits [2:0] are ignored.
[2:0] - Maximum allowed memory frequency.
3b111 - up to DDR-1066 (4 x 266)
3b110 - up to DDR-1333 (5 x 266)
3b101 - up to DDR-1600 (6 x 266)
3b100 - up to DDR-1866 (7 x 266)
[2:0] - Maximum allowed memory frequency.
3b111 - up to DDR-1066 (4 x 266)
3b110 - up to DDR-1333 (5 x 266)
3b101 - up to DDR-1600 (6 x 266)
3b100 - up to DDR-1866 (7 x 266)
3b011 - up to DDR-2133 (8 x 266) -- reserved, not supported
3b010 - up to DDR-2400 (9 x 266) -- reserved, not supported
3b001 - up to DDR-2666 (10 x 266) -- reserved, not supported
3b000 - up to DDR-2933 (11 x 266) -- reserved, not supported
3b010 - up to DDR-2400 (9 x 266) -- reserved, not supported
3b001 - up to DDR-2666 (10 x 266) -- reserved, not supported
3b000 - up to DDR-2933 (11 x 266) -- reserved, not supported
25:23
RO_FW
0x0
MEM_PA_SIZE:
Physical address size supported in the core low two bits (Assuming uncore is 44
by default)
000: 46
010: 44
101: 36
110: 40
111: 39
reserved
High order bit was the “do fault” bit it is not currently hooked up MUST MATCH
000: 46
010: 44
101: 36
110: 40
111: 39
reserved
High order bit was the “do fault” bit it is not currently hooked up MUST MATCH
UNCORE MISC, IFF exists
22:17
RO_FW
0x0
SSKU_P0_RATIO:
16:11
RO_FW
0x0
SSKU_P1_RATIO:
10:10
RV
-
Reserved
9:9
RO_FW
0x0
QOS_DIS:
Disable Quality of Service
8:8
RV
-
Reserved