Intel E7-8891 v2 CM8063601377422 Manual De Usuario
Los códigos de productos
CM8063601377422
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
257
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
This register controls behavior upon detection of errors.
14.2.80 RPERRSTS
Root Port Error Status.
The Root Error Status register reports status of error Messages (ERR_COR),
ERR_NONFATAL, and ERR_FATAL) received by the Root Complex in IIO, and errors
detected by the Root Port itself (which are treated conceptually as if the Root Port had
sent an error Message to itself). The ERR_NONFATAL and ERR_FATAL Messages are
grouped together as uncorrectable. Each correctable and uncorrectable (Nonfatal and
Fatal) error source has a first error bit and a next error bit associated with it
respectively. When an error is received by a Root Complex, the respective first error bit
is set and the Requestor ID is logged in the Error Source Identification register. A set
individual error status bit indicates that a particular error category occurred; software
may clear an error status by writing a 1 to the respective bit. If software does not clear
the first reported error before another error Message is received of the same category
(correctable or uncorrectable), the corresponding next error status bit will be set but
the Requestor ID of the subsequent error Message is discarded. The next error status
bits may be cleared by software by writing a 1 to the respective bit as well.
ERR_NONFATAL, and ERR_FATAL) received by the Root Complex in IIO, and errors
detected by the Root Port itself (which are treated conceptually as if the Root Port had
sent an error Message to itself). The ERR_NONFATAL and ERR_FATAL Messages are
grouped together as uncorrectable. Each correctable and uncorrectable (Nonfatal and
Fatal) error source has a first error bit and a next error bit associated with it
respectively. When an error is received by a Root Complex, the respective first error bit
is set and the Requestor ID is logged in the Error Source Identification register. A set
individual error status bit indicates that a particular error category occurred; software
may clear an error status by writing a 1 to the respective bit. If software does not clear
the first reported error before another error Message is received of the same category
(correctable or uncorrectable), the corresponding next error status bit will be set but
the Requestor ID of the subsequent error Message is discarded. The next error status
bits may be cleared by software by writing a 1 to the respective bit as well.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x174
Bit
Attr
Default
Description
31:3
RV
-
Reserved.
2:2
RW
0x0
fatal_error_reporting_enable:
Applies to root ports only. Enable MSI/INTx interrupt on fatal errors when set.
1:1
RW
0x0
non_fatal_error_reporting_enable:
Applies to root ports only. Enable interrupt on a nonfatal error when set.
0:0
RW
0x0
correctable_error_reporting_enable:
Applies to root ports only. Enable interrupt on correctable errors when set.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x178
Bit
Attr
Default
Description
31:27
RO
0x0
advanced_error_interrupt_message_number:
Advanced Error Interrupt Message Number offset between base message
data an the MSI message if assigned more than one message number. IIO
hardware automatically updates this register to 0x1h if the number of
messages allocated to the root port is 2.
26:7
RV
-
Reserved.
6:6
RW1CS
0x0
fatal_error_messages_received:
Set when one or more Fatal Uncorrectable error Messages have been
received.