Intel E7-8891 v2 CM8063601377422 Manual De Usuario

268

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

PCI Express Error Injection Capability Header.

PCI Express Error Injection Control Register.

31:20

RO

0xa

vseclen:

Vendor Specific Capability Length  
Indicates the length of the capability structure, including header bytes.

19:16

RO

0x1

vsecrev:

Vendor Specific Capability Revision 
Set to 1h for this version of the WHEA Error Injection logic.

15:0

RO

0x3

vsecid:

Vendor Specific ID  
Assigned for WHEA Error Injection

15:3

RV

-

Reserved.

2:2

RW

0x0

cause_ctoerr:

Cause a Completion Timeout Error  
When this bit is written to transition from 0 to 1, one and only one error 

assertion pulse is produced on the error source signal for the given port. This 

error will appear equivalent to an actual error assertion because this event is 

OR’d into the existing error reporting structure. To log another error, this bit 

must be cleared first, before setting again. Leaving this bit in a 1 state does 

not produce a persistent error condition.

Note:
This bit is used for an uncorrectable error test
This bit must be cleared by software before creating another event.
This bit is disabled by bit 0 of this register