Intel E7-8891 v2 CM8063601377422 Manual De Usuario

312

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

15:15

RW1C

0x0

dpe:

This bit is set by a device when it receives a packet on the primary side with 

an uncorrectable data error or an uncorrectable address/control parity error. 

The setting of this bit is regardless of the Parity Error Response bit (PERRE) 

in the PCICMD register.

14:14

RO

0x0

sse:

N/A for Intel® Quick Data DMA

13:13

RO

0x0

rma:

Intel® Quick Data DMA never sets this bit.

12:12

RO

0x0

rta:

Intel® Quick Data DMA never sets this bit.

11:11

RW1C

0x0

sta:

Intel® Quick Data DMA sets this bit when it receives 
a) memory transactions larger than a QWORD or crosses a QWORD 

boundary or 
b) config transactions larger than a DWORD or cross a DWORD boundary.

10:9

RO

0x0

devsel_timing:

Not applicable to PCI Express. Hardwired to 0.

8:8

RW1C

0x0

mdpe:

This bit is set by Intel® Quick Data DMA if the Parity Error Response bit in 

the PCI Command register is set and it receives a completion with poisoned 

data from the internal bus or if it forwards a packet with data (including MSI 

writes) to the internal bus with poison.

7:7

RO

0x0

fast_back_to_back:

Not applicable to PCI Express. Hardwired to 0.

6:6

RV

-

Reserved. 

5:5

RO

0x0

pci66mhz_capable:

Not applicable to PCI Express. Hardwired to 0.

4:4

RO

0x1

capabilities_list:

This bit indicates the presence of a capabilities list structure