Intel E7-8891 v2 CM8063601377422 Manual De Usuario

330

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

12:12

RW1CS

0x0

cmp_addr_err:

Completion Address Error. The DMA channel sets this bit 

indicating that the completion address register was configured 

to an illegal address or has not been configured.

11:11

RW1CS

0x0

desc_len_err:

Descriptor Length Error. The DMA channel sets this bit 

indicating that the current transfer has an illegal length field 

value. When this bit has been set, the address of the failed 

descriptor is in the Channel Status register.

10:10

RW1CS

0x0

desc_ctrl_err:

Descriptor Control Error. The DMA channel sets this bit 

indicating that the current transfer has an illegal control field 

value. When this bit has been set, the address of the failed 

descriptor is in the Channel Status register.

9:9

RW1CS

0x0

wr_data_err:

Write Data Error. The DMA channel sets this bit indicating that 

the current transfer has encountered an error while writing the 

destination data. This error could be because of an internal ram 

error in the write queue that stores the write data before being 

written to main memory. When this bit has been set, the 

address of the failed descriptor is in the Channel Status 

register.

8:8

RW1CS

0x0

rd_data_err:

Read Data Error. The DMA channel sets this bit indicating that 

the current transfer has encountered an error while accessing 

the source data. This error could be a read data that is received 

poisoned. When this bit has been set, the address of the failed 

descriptor is in the Channel Status register.

7:7

RW1CS

0x0

dma_data_parerr:

DMA Data Parity Error. The DMA channel sets this bit indicating 

that the current transfer has encountered an uncorrectable 

ECC/parity error reported by the DMA engine.

6:6

RW1CS

0x0

cdata_parerr:

Data Parity Error. The DMA channel sets this bit indicating that 

the current transfer has encountered a parity error. When this 

bit has been set, the address of the failed descriptor is in the 

Channel Status register.

5:5

RW1CS

0x0

chancmd_err:

CHANCMD Error. The DMA channel sets this bit indicating that a 

write to the CHANCMD register contained an invalid value (e.g. 

more than one command bit set).

4:4

RW1CS

0x0

chn_addr_valerr:

Chain Address Value Error. The DMA channel sets this bit 

indicating that the CHAINADDR register has an illegal address 

including an alignment error (not on a 64-byte boundary).