Intel E7-8891 v2 CM8063601377422 Manual De Usuario
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CM8063601377422
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
35
Datasheet Volume Two: Functional Description, February 2014
Home Agent Functional Description
4
Home Agent Functional
Description
The Intel Xeon processor E7 v2 product family supports up to two Home Agents (HA)
on-die. The HA is responsible for handling all DRAM requests homed at its node. It
accepts incoming home requests, snoop responses, and write back messages from the
ring, and in turn it sends data, completion, and snoop packets to the ring. The
aggregate of HAs enforce the memory coherency for the system. The HA also schedules
memory access requests to the local integrated memory controller (iMC) for DDR
memory reads and writes. After a requested memory access is completed, the HA
sends the corresponding response message back to the requester.
on-die. The HA is responsible for handling all DRAM requests homed at its node. It
accepts incoming home requests, snoop responses, and write back messages from the
ring, and in turn it sends data, completion, and snoop packets to the ring. The
aggregate of HAs enforce the memory coherency for the system. The HA also schedules
memory access requests to the local integrated memory controller (iMC) for DDR
memory reads and writes. After a requested memory access is completed, the HA
sends the corresponding response message back to the requester.
The implementation of the HA is closely tied to the Ring and the iMC. The ring stop in
the HA implements the necessary flow control and credit exchange for the messages
that are sent and received at HA. The HA interface to the iMC is responsible for the
memory access scheduling. The memory access scheduler, error handler, and
transaction control logic in the HA also support DRAM RAS features such as the
memory channel mirroring, DDR channel lockstep, and memory access retry. The Intel
Xeon processor E7 v2 product family will support channel mirroring, cross-socket HA
memory migration (no migration within socket HAs is allowed), Intel SMI2 channel -
retry and support for viral error conditions.
the HA implements the necessary flow control and credit exchange for the messages
that are sent and received at HA. The HA interface to the iMC is responsible for the
memory access scheduling. The memory access scheduler, error handler, and
transaction control logic in the HA also support DRAM RAS features such as the
memory channel mirroring, DDR channel lockstep, and memory access retry. The Intel
Xeon processor E7 v2 product family will support channel mirroring, cross-socket HA
memory migration (no migration within socket HAs is allowed), Intel SMI2 channel -
retry and support for viral error conditions.
4.1
Home Agent Architecture Overview
There are below primary parts of the Home Agent:
1) Ring interface for Home Agent
2) Backup Tracker (BT) and Home Tracker (HT)
3) Intel QPI home control logic
4) Home Agent Data Buffer (HADB)
5) Memory controller interface.
4.1.1
Ring Interface for Home Agent
The ring interface is used for Intel QPI protocol packet communication to and from the
HA.
HA.
4.1.2
Backup Tracker and Home Tracker
The HA contains a tracker, which is a pool of pre-allocated buffers for tracking system
requests. The Intel Xeon processor E7 v2 product family HA implements a 128-entry In
flight Memory Buffer (also called Home tracker, HT), a 512-entry Tracker (also called
Backup Tracker, BT).
requests. The Intel Xeon processor E7 v2 product family HA implements a 128-entry In
flight Memory Buffer (also called Home tracker, HT), a 512-entry Tracker (also called
Backup Tracker, BT).