Intel E7-8891 v2 CM8063601377422 Manual De Usuario

402

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

Extended Intel

®

VT-d Capability.

33:24

RO

0x10

fault_recording_register_offset:

Fault registers are at offset 100h 

23:23

RO

0x0

spatial_separation:

22:22

RO

0x1

zlr:

Zero-length DMA requests to write-only pages supported.

21:16

RO_V

0x2f

mgaw:

This register is set by the processor-based on the setting of the GPA_LIMIT 

register. The value is the same for both the VT and non-VT engines. This is 

because the translation for VT has been extended to be 4-level (instead of 3).

15:13

RV

-

Reserved.

12:8

RO

0x4

sagaw:

Supports 4-level walk on both VT and non-VT engines

7:7

RO

0x0

tcm:

The processor does not cache invalid pages.
This bit should always be set to 0 on HW. It can be set to one when we are 

doing software virtualization of Intel

®

VT-d. 

6:6

RO

0x1

phmr_support:

The processor supports protected high memory range.

5:5

RO

0x1

plmr_support:

The processor supports protected low memory range.

4:4

RO

0x0

rwbf:

N/A to processor.

3:3

RO

0x0

advanced_fault_logging:

The processor does not support advanced fault logging.

2:0

RO

0x6

number_of_domains_supported:

The processor supports 256 domains with 8 bit domain ID.

63:24

RV

-

Reserved.