Intel J1850 FH8065301455200 Manual De Usuario
Los códigos de productos
FH8065301455200
Datasheet
1255
PCU – iLB – 8259 Programmable Interrupt Controllers (PIC)
internal INTA# pulse to freeze the state of the interrupts for priority resolution. On the
second INTA# pulse, the master or slave sends the interrupt vector to the processor
with the acknowledged interrupt code. This code is based upon the ICW2.IVBA bits,
combined with the ICW2.IRL bits representing the interrupt within that controller.
second INTA# pulse, the master or slave sends the interrupt vector to the processor
with the acknowledged interrupt code. This code is based upon the ICW2.IVBA bits,
combined with the ICW2.IRL bits representing the interrupt within that controller.
Note:
References to ICWx and OCWx registers are relevant to both the master and slave
8259 controllers.
8259 controllers.
31.1.1.3
Hardware/Software Interrupt Sequence
1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or
seen high in level mode, setting the corresponding IRR bit.
2. The PIC sends INTR active to the processor if an asserted interrupt is not masked.
3. The processor acknowledges the INTR and responds with an interrupt acknowledge
cycle.
4. Upon observing the special cycle, the processor converts it into the two cycles that
the internal 8259 pair can respond to. Each cycle appears as an interrupt
acknowledge pulse on the internal INTA# pin of the cascaded interrupt controllers.
acknowledge pulse on the internal INTA# pin of the cascaded interrupt controllers.
5. Upon receiving the first internally generated INTA# pulse, the highest priority ISR
bit is set and the corresponding IRR bit is reset. On the trailing edge of the first
pulse, a slave identification code is broadcast by the master to the slave on a
private, internal three bit wide bus. The slave controller uses these bits to
determine if it must respond with an interrupt vector during the second INTA#
pulse.
pulse, a slave identification code is broadcast by the master to the slave on a
private, internal three bit wide bus. The slave controller uses these bits to
determine if it must respond with an interrupt vector during the second INTA#
pulse.
6. Upon receiving the second internally generated INTA# pulse, the PIC returns the
interrupt vector. If no interrupt request is present because the request was too
short in duration, the PIC returns vector 7 from the master controller.
short in duration, the PIC returns vector 7 from the master controller.
7. This completes the interrupt cycle. In AEOI mode the ISR bit is reset at the end of
the second INTA# pulse. Otherwise, the ISR bit remains set until an appropriate
EOI command is issued at the end of the interrupt subroutine.
EOI command is issued at the end of the interrupt subroutine.
Table 190. Content of Interrupt Vector Byte
Master, Slave Interrupt
Bits [7:3]
Bits [2:0]
IRQ7,15
ICW2.IVBA
111
IRQ6,14
110
IRQ5,13
101
IRQ4,12
100
IRQ3,11
011
IRQ2,10
010
IRQ1,9
001
IRQ0,8
000