Acer E3-1220 v3 KC.12201.3E3 Manual De Usuario

performance of fine-grain locking while actually programming using coarse-grain

locks. Details on Intel TSX may be found in Intel

The x2APIC architecture extends the xAPIC architecture that provides key

mechanisms for interrupt delivery. This extension is primarily intended to increase

processor addressability.

Specifically, x2APIC:
•

Retains all key elements of compatibility to the xAPIC architecture:
— Delivery modes
— Interrupt and processor priorities
— Interrupt sources
— Interrupt destination types

•

Provides extensions to scale processor addressability for both the logical and

physical destination modes

•

Adds new features to enhance performance of interrupt delivery

•

Reduces complexity of logical destination mode interrupt delivery on link based

architectures

The key enhancements provided by the x2APIC architecture over xAPIC are the

following:
•

Support for two modes of operation to provide backward compatibility and

extensibility for future platform innovations:
— In xAPIC compatibility mode, APIC registers are accessed through memory

mapped interface to a 4K-Byte page, identical to the xAPIC architecture.

— In x2APIC mode, APIC registers are accessed through Model Specific Register

(MSR) interfaces. In this mode, the x2APIC architecture provides significantly

increased processor addressability and some enhancements on interrupt

delivery.

•

Increased range of processor addressability in x2APIC mode:
— Physical xAPIC ID field increases from 8 bits to 32 bits, allowing for interrupt

processor addressability up to 4G–1 processors in physical destination mode.

A processor implementation of x2APIC architecture can support fewer than 32-

bits in a software transparent fashion.

— Logical xAPIC ID field increases from 8 bits to 32 bits. The 32-bit logical

x2APIC ID is partitioned into two sub-fields – a 16-bit cluster ID and a 16-bit

logical ID within the cluster. Consequently, ((2^20) – 16) processors can be

addressed in logical destination mode. Processor implementations can support

fewer than 16 bits in the cluster ID sub-field and logical ID sub-field in a

software agnostic fashion.

•

More efficient MSR interface to access APIC registers:
— To enhance inter-processor and self-directed interrupt delivery as well as the

ability to virtualize the local APIC, the APIC register set can be accessed only

through MSR-based interfaces in x2APIC mode. The Memory Mapped IO

(MMIO) interface used by xAPIC is not supported in x2APIC mode.

Intel

®

 Xeon

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 Processor E3-1200 v3 Product Family

Datasheet – Volume 1 of 2

June 2013

46

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