Acer E3-1220 v3 KC.12201.3E3 Manual De Usuario

Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or

an MWAIT(C6) instruction. Before entering core C6 state, the core will save its

architectural state to a dedicated SRAM. Once complete, a core will have its voltage

reduced to zero volts. During exit, the core is powered on and its architectural state is

restored.

Individual threads of a core can enter the C7 state by initiating a P_LVL4 I/O read to

the P_BLK or by an MWAIT(C7) instruction. The core C7 state exhibits the same

behavior as the core C6 state.

C7 state may not be available on all SKUs.

In general, deeper C-states, such as C6 state, have long latencies and have higher

energy entry/exit costs. The resulting performance and energy penalties become

significant when the entry/exit frequency of a deeper C-state is high. Therefore,

incorrect or inefficient usage of deeper C-states have a negative impact on idle power.

To increase residency and improve idle power in deeper C-states, the processor

supports C-state auto-demotion.

There are two C-state auto-demotion options:
•

C7/C6 to C3 state

•

C7/C6/C3 To C1 state

The decision to demote a core from C6/C7 to C3 or C3/C6/C7 to C1 state is based on

each core’s immediate residency history and interrupt rate . If the interrupt rate

experienced on a core is high and the residence in a deep C-state between such

interrupts is low, the core can be demoted to a C3 or C1 state. A higher interrupt

pattern is required to demote a core to C1 state as compared to C3 state.

This feature is disabled by default. BIOS must enable it in the

PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by

this register.

The processor supports C0, C1/C1E, C3, C6, and C7 (on some SKUs) power states.

The following is a summary of the general rules for package C-state entry. These

apply to all package C-states, unless specified otherwise:
•

A package C-state request is determined by the lowest numerical core C-state

amongst all cores.

•

A package C-state is automatically resolved by the processor depending on the

core idle power states and the status of the platform components.
— Each core can be at a lower idle power state than the package if the platform

does not grant the processor permission to enter a requested package C-state.

— The platform may allow additional power savings to be realized in the

processor.

Intel

®

 Xeon

®

 Processor E3-1200 v3 Product Family

Datasheet – Volume 1 of 2

June 2013

54

Order No.: 328907-001