Intel B810 FF8062700848800 Manual De Usuario
Los códigos de productos
FF8062700848800
Intel
®
Celeron
®
Processor on 0.13 Micron Process in the 478-Pin Package Datasheet
41
System Bus Signal Quality Specifications
System Bus Signal Quality
Specifications
Specifications
3
Source synchronous data transfer requires the clean reception of data signals and their associated
strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage
swing will adversely affect system timings. Ringback and signal non-monotinicity cannot be
tolerated since these phenomena may inadvertently advance receiver state machines. Excessive
signal swings (overshoot and undershoot) are detrimental to silicon gate oxide integrity, and can
cause device failure if absolute voltage limits are exceeded. Additionally, overshoot and
undershoot can cause timing degradation due to the build up of inter-symbol interference (ISI)
effects. For these reasons, it is important that the designer work to achieve a solution that provides
acceptable signal quality across all systematic variations encountered in volume manufacturing.
strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage
swing will adversely affect system timings. Ringback and signal non-monotinicity cannot be
tolerated since these phenomena may inadvertently advance receiver state machines. Excessive
signal swings (overshoot and undershoot) are detrimental to silicon gate oxide integrity, and can
cause device failure if absolute voltage limits are exceeded. Additionally, overshoot and
undershoot can cause timing degradation due to the build up of inter-symbol interference (ISI)
effects. For these reasons, it is important that the designer work to achieve a solution that provides
acceptable signal quality across all systematic variations encountered in volume manufacturing.
This section documents signal quality metrics used to derive topology and routing guidelines
through simulation and for interpreting results for signal quality measurements of actual designs.
through simulation and for interpreting results for signal quality measurements of actual designs.
3.1
System Bus Clock (BCLK) Signal Quality
Specifications
Specifications
describes the signal quality specifications at the processor core silicon for the processor
system bus clock (BCLK) signals.
describes the signal quality waveform for the system
bus clock at the processor core silicon.
Table 23. BCLK Signal Quality Specifications
Parameter
Min
Max
Unit
Figure
Notes
1
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all Celeron processor on 0.13 micron process
frequencies.
frequencies.
BCLK[1:0] Overshoot
N/A
0.30
V
BCLK[1:0] Undershoot
N/A
0.30
V
BCLK[1:0] Ringback Margin
0.20
N/A
V
2
2.
The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal can dip back to after passing the V
voltage the BCLK signal can dip back to after passing the V
IH
(rising) or V
IL
(falling) voltage limits. This spec-
ification is an absolute value.
BCLK[1:0] Threshold Region
N/A
0.10
V