Corsair 512 MB DDR2 Server Memory Module CM72DD512AR-400/S Manual De Usuario
Los códigos de productos
CM72DD512AR-400/S
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
73, 74, 192
RAS#, CAS#,
WE#
WE#
Input
Command Inputs: RAS#, CAS#, and WE# (along with S#) define the
command being entered.
command being entered.
71, 190
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0
and BA1 define which mode register including MR, EMR, EMR(2), and
EMR(3) is loaded during the LOAD MODE command.
ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0
and BA1 define which mode register including MR, EMR, EMR(2), and
EMR(3) is loaded during the LOAD MODE command.
57, 58, 60, 61, 63, 70, 176,
177, 179, 180, 182, 183,
188, 196
177, 179, 180, 182, 183,
188, 196
A0-A12
(512MB), A0-
A13 (1GB)
(512MB), A0-
A13 (1GB)
Input
Address Inputs: Provide the row address for ACTIVE commands, and
the column address and auto precharge bit (A10) for Read/Write
commands, to select one location out of the memory array in the
respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10
LOW, device bank selected by BA0, BA1) or all device banks (A10
HIGH). The address inputs also provide the opcode during a LOAD
MODE command.
the column address and auto precharge bit (A10) for Read/Write
commands, to select one location out of the memory array in the
respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10
LOW, device bank selected by BA0, BA1) or all device banks (A10
HIGH). The address inputs also provide the opcode during a LOAD
MODE command.
3, 4, 9, 10, 12, 13, 21, 22, 24,
25, 30, 31, 33, 34, 39, 40,
80, 81, 86, 87, 89, 90, 95,
96, 98, 99, 107, 108, 110,
111, 116, 117, 122, 123,
128, 129, 131, 132, 140,
141, 143, 144, 149, 150,
152, 153, 158, 159, 199,
200, 205, 206, 208, 209,
214, 215, 217, 218, 226,
227, 229, 230, 235, 236
25, 30, 31, 33, 34, 39, 40,
80, 81, 86, 87, 89, 90, 95,
96, 98, 99, 107, 108, 110,
111, 116, 117, 122, 123,
128, 129, 131, 132, 140,
141, 143, 144, 149, 150,
152, 153, 158, 159, 199,
200, 205, 206, 208, 209,
214, 215, 217, 218, 226,
227, 229, 230, 235, 236
DQ0-DQ63
I/O
Data Input/Output: Bidirectional data bus.
6, 7, 15, 16, 27, 28, 36, 37,
45, 46, 83, 84, 92, 93, 104,
105, 113, 114, 125, 126,
134, 135, 146, 147, 155,
156, 164, 165, 202, 203,
211, 212, 223, 224, 232,
233
45, 46, 83, 84, 92, 93, 104,
105, 113, 114, 125, 126,
134, 135, 146, 147, 155,
156, 164, 165, 202, 203,
211, 212, 223, 224, 232,
233
DQS0-
DQS17,
DQS0#-
DQS17#
DQS17,
DQS0#-
DQS17#
I/O
Data Strobe: Output with read data, input with write data for sourece
synchronous operation. Edge-aligned with read data, center aligned
with write data. DQS# is only used when differential data strobe mode
is enabled via the LOAD MODE command.
synchronous operation. Edge-aligned with read data, center aligned
with write data. DQS# is only used when differential data strobe mode
is enabled via the LOAD MODE command.
42, 43, 48, 49, 161, 162,
167, 168
167, 168
CB0-CB7
I/O
Check Bits: ECC, 1-bit error detection and correction.
120
SCL
Input
Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect device.
presence-detect device.
101, 239, 240
SA0-SA2
Input
Presence-Detect Address Inputs: These pins are used to configure the
presence-detect device.
presence-detect device.
119
SDA
Input/Outpu
t
t
Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer
addresses and data into and out of the presence-detect portion of the
module.
addresses and data into and out of the presence-detect portion of the
module.
18
RESET#
Input
Asynchronously forces all registered outputs LOW when RESET# is
LOW. This signal can be used during power up to ensure that CKE is
LOW and DQs are High-Z.
LOW. This signal can be used during power up to ensure that CKE is
LOW and DQs are High-Z.
53, 59, 64, 67, 69, 172, 178,
184, 187, 189, 197
184, 187, 189, 197
VDD
Supply
Power Supply: 1.8V +/-0.1V
51, 56, 62, 72, 75, 78, 170,
175, 181, 191, 194
175, 181, 191, 194
VDDQ
Supply
DQ Power Supply: 1.8V +/-0.1V. Isolated on the device for improved
noise immunity.
noise immunity.
1
VREF
Supply
SSTL_18 reference voltage.
2, 5, 8, 11, 14, 17, 20, 23, 26,
29, 32, 35, 38, 41, 44, 47,
50, 65, 66, 79, 82, 85, 88,
91, 94, 97, 100, 103, 106,
109, 112, 115, 118, 121,
124, 127, 130, 133, 136,
139, 142, 145, 148, 151,
154, 157, 160, 163, 166,
169, 198, 201, 204, 207,
210, 213, 216, 219, 222,
225, 228, 231, 234, 237
29, 32, 35, 38, 41, 44, 47,
50, 65, 66, 79, 82, 85, 88,
91, 94, 97, 100, 103, 106,
109, 112, 115, 118, 121,
124, 127, 130, 133, 136,
139, 142, 145, 148, 151,
154, 157, 160, 163, 166,
169, 198, 201, 204, 207,
210, 213, 216, 219, 222,
225, 228, 231, 234, 237
VSS
Supply
Ground.
238
VDDSPD
Supply
Serial EEPROM positive power supply: +1.7V to +3.6V.
19, 54 (512MB, 1GB), 55,
68, 76, 77, 102, 171, 196
(512MB), 173, 174
68, 76, 77, 102, 171, 196
(512MB), 173, 174
NC
-
No Connect: These pins should be left unconnected.
137, 138, 220, 221
RFU
-
Reserved for Future Use
Page 3
512 MB DDR2 Server Memory Module
Pin Confi guration