Bourns PROT-OVER VOLT/TISP61521DR-S/8-SOIC TISP61521DR-S Hoja De Datos

JULY 2010 - REVISED MAY 2012

Specifi cations are subject to change without notice.

Customers should verify actual device performance in their specifi c applications.

Repetitive peak off-state voltage, I

G

 

C

°

 

0

4

-

0

 

=

 

≤

 T

J

≤

 85 °C

V

DRM

-170

V

V

Repetitive peak gate-cathode voltage, V

KA

 

C

°

 

0

4

-

0

 

=

 

≤

 T

J

≤

 85 °C V

GKRM

 -167

Non-repetitive peak on-state pulse current (see Notes 1 and 2)

I

TSP

30
40

120

A

 85

Non-repetitive peak on-state current, 60 Hz (see Notes 1, 2 and 3)

I

TSM

0.5

A

900 s

Non-repetitive peak ga

I

)

2

 

d

n

a

 

1

 

s

e

t

o

N

 

e

e

s

(

 

d

e

n

o

m

m

o

c

 

s

e

d

o

h

t

a

c

 

,

e

s

l

u

p

 

s

µ

 

0

1

/

2

 

,

t

n

e

r

r

u

c

 

e

t

GSM

40

A

Junction temperature

T

J

-40 to +150

°C

Storage temperature range

T

stg

-40 to +150

°C

NOTES: 1. Initially the protector must be in thermal equilibrium with T

J

 = 25 °C.  The surge may be repeated after the device returns to its initial

conditions.

2. These non-repetitive rated currents are peak values for either polarity. The rated current values may be applied to any cathode-

anode terminal pair. Additionally, all cathode-anode terminal pairs may have their rated current values applied simultaneously (in
this case the anode terminal current will be four times the rated current value of an individual terminal pair).

3. EIA/JESD51-2 environment and EIA/JESD51-7 high effective thermal conductivity test board (multi-layer) connected with 0.6 mm

printed wiring track widths.

C

G

Gate decoupling capacitor

100

nF

I

D

Off-state current

V

D

 = V

DRM

, V

GK

 = 0

-5

µA

V

(BO)

Breakover voltage

10/700 µs, I

T

 = -40 A, R

S

 = 55 

Ω,  V

GG

 = -48 V,

 C

G

V

4

6

-

F

n

0

0

1

 

=

 

V

F

Forward voltage

I

F

 = 5 A, t

w

 = 200 µs

3

V

V

FRM

Peak forward recovery 

voltage

10/700 µs, I

F

 = 40 A,

 R

S

 = 55 

Ω, V

GG

 = -48 V, C

G

V

2

1

F

n

0

0

1

 

=

 

I

H

Holding current

I

T

= -1 A,  di/dt = 1 A/ms,  V

GG

A

m

0

5

1

-

100 V

-

 

=

 

I

GAS

Gate reverse current

V

GG

= V

GK

 = V

GKRM

, V

KA

A

µ

5

-

0

 

=

 

I

GT

Gate trigger current

I

T

 = 3 A, t

p(g)

≥ 20 µs, V

GG

A

m

5

 

100 V

-

 

=

 

V

GT

Gate trigger voltage

I

T

 = 3 A, t

p(g)

≥ 20 µs, V

GG

V

5

.

2

100 V

-

 

=

 

C

AK

Anode-cathode off-state 

capacitance

f = 1 MHz, V

d

 = 1 V I

G

 = 0, (see Note 5)

V

D

 = -3 V

100

pF

V

D

= -48 V

50

NOTE:

5. These capacitance measurements employ a three terminal capacitance bridge incorporating a guard circuit.  The unmeasured

device terminals are a.c. connected to the guard terminal of the bridge.

10/1000 µs (Bellcore GR-1089-CORE, Issue 1, November 1994, Section 4)
5/310 µs (ITU-T K.20/21/45, YD/T-950, open circuit voltage waveshape 10/700)

2/10 µs (Bellcore GR-1089-CORE, Issue 1, November 1994, Section 4)

2/40 µs (IEC61000-4-5, 1.2/50 µs open circuit voltage, 2 ohm + 10 ohm, see Note 4) 

4. Combination wave generator as specified in ITU-T K.20, K.21, K.44.