Microchip Technology MCU PIC10F322T-I/OT SOT-23-6 MCP PIC10F322T-I/OT Hoja De Datos
Los códigos de productos
PIC10F322T-I/OT
2011 Microchip Technology Inc.
Preliminary
DS41585A-page 103
PIC10(L)F320/322
REGISTER 16-1:
OPTION_REG: OPTION REGISTER
R/W-1/u
R/W-1/u
R/W-1/u
R/W-1/u
R/W-1/u
R/W-1/u
R/W-1/u
R/W-1/u
WPUEN
INTEDG
T0CS
T0SE
PSA
PS<2:0>
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
WPUEN:
Weak Pull-up Enable bit
(1)
1
= Weak pull-ups are disabled
0
= Weak pull-ups are enabled by individual PORT latch values
bit 6
INTEDG:
Interrupt Edge Select bit
1
= Interrupt on rising edge of INT pin
0
= Interrupt on falling edge of INT pin
bit 5
T0CS:
TMR0 Clock Source Select bit
1
= Transition on T0CKI pin
0
= Internal instruction cycle clock (F
OSC
/4)
bit 4
T0SE:
TMR0 Source Edge Select bit
1
= Increment on high-to-low transition on T0CKI pin
0
= Increment on low-to-high transition on T0CKI pin
bit 3
PSA:
Prescaler Assignment bit
1
= Prescaler is inactive and has no effect on the Timer 0 module
0
= Prescaler is assigned to the Timer0 module
bit 2-0
PS<2:0>:
Prescaler Rate Select bits
Note 1:
WPUEN does not disable the pull-up for the MCLR input when MCLR = 1.
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Bit Value
TMR0 Rate
TABLE 16-1:
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
OPTION_REG WPUEN INTEDG
T0CS
T0SE
PSA
PS<2:0>
TMR0
Timer0 module Register
TRISA
—
—
—
—
—
TRISA2
TRISA1
TRISA0
Legend:
– = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the
Timer0 module.
Timer0 module.