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PIC18F87K22-I/PTRSL
PIC18F87K22 FAMILY
DS39960D-page 112
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FIGURE 7-2:
TABLE WRITE OPERATION
7.2
Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
the TBLRD and TBLWT instructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
7.2.1
EECON1 AND EECON2 REGISTERS
The EECON1 register (
) is the control
register for memory accesses. The EECON2 register,
not a physical register, is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.
The EEPGD control bit determines if the access is a
program or data EEPROM memory access. When
clear, any subsequent operations operate on the data
EEPROM memory. When set, any subsequent
operations operate on the program memory.
The CFGS control bit determines if the access is to the
Configuration/Calibration registers or to program
memory/data EEPROM memory. When set,
subsequent operations operate on Configuration
registers regardless of EEPGD (see
not a physical register, is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.
The EEPGD control bit determines if the access is a
program or data EEPROM memory access. When
clear, any subsequent operations operate on the data
EEPROM memory. When set, any subsequent
operations operate on the program memory.
The CFGS control bit determines if the access is to the
Configuration/Calibration registers or to program
memory/data EEPROM memory. When set,
subsequent operations operate on Configuration
registers regardless of EEPGD (see
). When clear, memory
selection access is determined by EEPGD.
The FREE bit, when set, allows a program memory
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
The WREN bit, when set, allows a write operation. On
power-up, the WREN bit is clear. The WRERR bit is set
in hardware when the WR bit is set and cleared when
the internal programming timer expires and the write
operation is complete.
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
The WREN bit, when set, allows a write operation. On
power-up, the WREN bit is clear. The WRERR bit is set
in hardware when the WR bit is set and cleared when
the internal programming timer expires and the write
operation is complete.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software. It is cleared in
hardware at the completion of the write operation.
cannot be cleared, only set, in software. It is cleared in
hardware at the completion of the write operation.
Table Pointer
(1)
Table Latch (8-bit)
TBLPTRH
TBLPTRL
TABLAT
Program Memory
(TBLPTR)
(TBLPTR)
TBLPTRU
Instruction:
TBLWT
*
Note 1:
The Table Pointer actually points to one of 64 holding registers; the address of which is determined by
TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in
TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in
.
Holding Registers
Program Memory
Note:
During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a Reset or a write operation was
attempted improperly.
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a Reset or a write operation was
attempted improperly.
Note:
The EEIF interrupt flag bit (PIR6<4>) is
set when the write is complete. It must be
cleared in software.
set when the write is complete. It must be
cleared in software.