Microchip Technology MCU PIC PIC18F87K22-I/PTRSL TQFP-80 MCP PIC18F87K22-I/PTRSL Hoja De Datos

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PIC18F87K22 FAMILY
DS39960D-page 180
 2009-2011 Microchip Technology Inc.
TABLE 12-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE     
    
RE7/ECCP2/
P2A/AD15
RE7
0
O
DIG
LATE<7> data output.
1
I
ST
PORTE<7> data input.
ECCP2
)
0
O
DIG
ECCP2 compare/PWM output; takes priority over port data.
1
I
ST
ECCP2 capture input.
P2A
0
O
ECCP2 PWM Output A.
May be configured for tri-state during Enhanced PWM shutdown event.
AD15
x
O
DIG
External memory interface, Address/Data Bit 15 output.
x
I
TTL
External memory interface, Data Bit 15 input.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTE
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
LATE
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0
TRISE
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
PADCFG1
RDPU
REPU
RJPU
(
)
RTSECSEL1 RTSECSEL0
ODCON1
SSP1OD
CCP2OD
CCP1OD
SSP2OD
ODCON2
CCP10OD
(
CCP9OD
(
)
CCP8OD
CCP7OD CCP6OD
CCP5OD
CCP4OD
CCP3OD
Legend:
Shaded cells are not used by PORTE.
Note 1:
Unimplemented on PIC18FX5K22 devices, read as ‘0’.
2:
Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
TABLE 12-9:
PORTE FUNCTIONS (CONTINUED)
Pin Name
Function
TRIS 
Setting
I/O
I/O 
Type
Description
Legend:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input, 
x
 = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note
1:
Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared and in Microcontroller mode.
2:
This feature is only available on PIC18F8XKXX devices.