Microchip Technology MCU PIC PIC18F87K22-I/PTRSL TQFP-80 MCP PIC18F87K22-I/PTRSL Hoja De Datos
Los códigos de productos
PIC18F87K22-I/PTRSL
2009-2011 Microchip Technology Inc.
DS39960D-page 545
PIC18F87K22 FAMILY
Associated Registers ................................................ 225
Interrupt..................................................................... 224
Operation .................................................................. 223
Output ....................................................................... 224
Postscaler. See Postscaler, Timer4/6/8/10/12.
Prescaler. See Prescaler, Timer4/6/8/10/12.
PRx Register............................................................. 223
TMRx Register .......................................................... 223
Interrupt..................................................................... 224
Operation .................................................................. 223
Output ....................................................................... 224
Postscaler. See Postscaler, Timer4/6/8/10/12.
Prescaler. See Prescaler, Timer4/6/8/10/12.
PRx Register............................................................. 223
TMRx Register .......................................................... 223
Timing Diagrams
A/D Conversion......................................................... 524
Asynchronous Reception .......................................... 341
Asynchronous Transmission..................................... 338
Asynchronous Transmission (Back-to-Back) ............ 338
Automatic Baud Rate Calculation ............................. 336
Auto-Wake-up Bit (WUE) During Normal
Asynchronous Reception .......................................... 341
Asynchronous Transmission..................................... 338
Asynchronous Transmission (Back-to-Back) ............ 338
Automatic Baud Rate Calculation ............................. 336
Auto-Wake-up Bit (WUE) During Normal
Auto-Wake-up Bit (WUE) During Sleep .................... 343
Baud Rate Generator with Clock Arbitration ............. 314
BRG Overflow Sequence.......................................... 336
BRG Reset Due to SDAx Arbitration During
Baud Rate Generator with Clock Arbitration ............. 314
BRG Overflow Sequence.......................................... 336
BRG Reset Due to SDAx Arbitration During
Brown-out Reset (BOR) ............................................ 509
Bus Collision During Repeated Start Condition
Bus Collision During Repeated Start Condition
Bus Collision During Start Condition (SCLx = 0) ...... 323
Bus Collision During Start Condition (SDAx Only).... 322
Bus Collision During Stop Condition (Case 1) .......... 325
Bus Collision During Stop Condition (Case 2) .......... 325
Bus Collision for Transmit and Acknowledge............ 321
Capture/Compare/PWM............................................ 513
CLKO and I/O ........................................................... 505
Clock Synchronization .............................................. 307
Clock/Instruction Cycle ............................................... 92
EUSART Synchronous Transmission
Bus Collision During Start Condition (SDAx Only).... 322
Bus Collision During Stop Condition (Case 1) .......... 325
Bus Collision During Stop Condition (Case 2) .......... 325
Bus Collision for Transmit and Acknowledge............ 321
Capture/Compare/PWM............................................ 513
CLKO and I/O ........................................................... 505
Clock Synchronization .............................................. 307
Clock/Instruction Cycle ............................................... 92
EUSART Synchronous Transmission
Example SPI Master Mode (CKE = 0) ...................... 514
Example SPI Master Mode (CKE = 1) ...................... 515
Example SPI Slave Mode (CKE = 0) ........................ 516
Example SPI Slave Mode (CKE = 1) ........................ 517
External Clock........................................................... 503
External Memory Bus for SLEEP (Extended
Example SPI Master Mode (CKE = 1) ...................... 515
Example SPI Slave Mode (CKE = 0) ........................ 516
Example SPI Slave Mode (CKE = 1) ........................ 517
External Clock........................................................... 503
External Memory Bus for SLEEP (Extended
Fail-Safe Clock Monitor (FSCM) ............................... 425
First Start Bit Timing ................................................. 315
Full-Bridge PWM Output ........................................... 270
Half-Bridge PWM Output .................................. 268, 275
High-Voltage Detect Operation (VDIRMAG = 1)....... 383
HLVD Characteristics................................................ 511
I
First Start Bit Timing ................................................. 315
Full-Bridge PWM Output ........................................... 270
Half-Bridge PWM Output .................................. 268, 275
High-Voltage Detect Operation (VDIRMAG = 1)....... 383
HLVD Characteristics................................................ 511
I
2
I
2
I
2
I
2
I
2
I
2
I
2
I
2
I
2
I
I
I
I
I
I
MSSP I
Parallel Slave Port (PSP) Read................................ 191
Parallel Slave Port (PSP) Write ................................ 190
Program Memory Fetch (8-bit) ................................. 506
Program Memory Read ............................................ 507
Program Memory Write ............................................ 508
PWM Auto-Shutdown with Auto-Restart Enabled
Parallel Slave Port (PSP) Write ................................ 190
Program Memory Fetch (8-bit) ................................. 506
Program Memory Read ............................................ 507
Program Memory Write ............................................ 508
PWM Auto-Shutdown with Auto-Restart Enabled
PWM Direction Change ............................................ 271
PWM Direction Change at Near 100%
PWM Direction Change at Near 100%
PWM Output ............................................................. 255
PWM Output (Active-High) ....................................... 266
PWM Output (Active-Low) ........................................ 267
Repeated Start Condition ......................................... 316
Reset, Watchdog Timer (WDT), Oscillator Start-up
PWM Output (Active-High) ....................................... 266
PWM Output (Active-Low) ........................................ 267
Repeated Start Condition ......................................... 316
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence............................. 344
Slave Synchronization .............................................. 287
Slow Rise Time (MCLR Tied to V
Slave Synchronization .............................................. 287
Slow Rise Time (MCLR Tied to V
DD
,
V
DD
Rise > T
PWRT
SPI Mode (Master Mode) ......................................... 286
SPI Mode (Slave Mode, CKE = 0) ............................ 288
SPI Mode (Slave Mode, CKE = 1) ............................ 288
Steering Event at Beginning of Instruction
SPI Mode (Slave Mode, CKE = 0) ............................ 288
SPI Mode (Slave Mode, CKE = 1) ............................ 288
Steering Event at Beginning of Instruction
Synchronous Reception (Master Mode, SREN) ....... 347
Synchronous Transmission ...................................... 345
Synchronous Transmission (Through TXEN)........... 346
Time-out Sequence on Power-up (MCLR
Synchronous Transmission ...................................... 345
Synchronous Transmission (Through TXEN)........... 346
Time-out Sequence on Power-up (MCLR
Not Tied to V
DD
Time-out Sequence on Power-up (MCLR
Not Tied to V
DD
Time-out Sequence on Power-up (MCLR
Tied to V
DD
, V
DD
Rise T
PWRT
Timer Pulse Generation............................................ 242
Timer0 and Timer1 External Clock ........................... 512
Timer1 Gate Count Enable Mode............................. 204
Timer1 Gate Single Pulse Mode............................... 206
Timer1 Gate Single Pulse/Toggle
Timer0 and Timer1 External Clock ........................... 512
Timer1 Gate Count Enable Mode............................. 204
Timer1 Gate Single Pulse Mode............................... 206
Timer1 Gate Single Pulse/Toggle