Microchip Technology MCU PIC PIC18F87K22-I/PTRSL TQFP-80 MCP PIC18F87K22-I/PTRSL Hoja De Datos
Los códigos de productos
PIC18F87K22-I/PTRSL
2009-2011 Microchip Technology Inc.
DS39960D-page 61
PIC18F87K22 FAMILY
Clocks to the device continue while the INTOSC source
stabilizes after an interval of T
stabilizes after an interval of T
IOBST
(Parameter
If the IRCF bits were previously at a non-zero value, or
if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, the HFIOFS or
MFIOFS bit will remain set.
if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, the HFIOFS or
MFIOFS bit will remain set.
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
primary clock becomes ready, a clock switch to the
primary clock occurs (see
the device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
primary clock becomes ready, a clock switch to the
primary clock occurs (see
). When the clock
switch is complete, the HFIOFS or MFIOFS bit is
cleared, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The LF-INTOSC source
will continue to run if either the WDT or the Fail-Safe
Clock Monitor is enabled.
cleared, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The LF-INTOSC source
will continue to run if either the WDT or the Fail-Safe
Clock Monitor is enabled.
FIGURE 4-3:
TRANSITION TIMING TO RC_RUN MODE
FIGURE 4-4:
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q4
Q3
Q2
OSC1
Peripheral
Program
Q1
LF-INTOSC
Q1
Counter
Clock
CPU
Clock
PC + 2
PC
1
2
3
n-1
n
Clock Transition
(1)
Q4
Q3
Q2
Q1
Q3
Q2
PC + 4
Note 1:
Clock transition typically occurs within 2-4 T
OSC
.
Q1
Q3 Q4
OSC1
Peripheral
Program
PC
INTOSC
PLL Clock
Q1
PC + 4
Q2
Output
Q3
Q4
Q1
CPU Clock
PC + 2
Clock
Counter
Q2
Q2
Q3
Note 1:
T
OST
= 1024 T
OSC
; T
PLL
= 2 ms (approx). These intervals are not shown to scale.
2:
Clock transition typically occurs within 2-4 T
OSC
.
SCS<1:0> bits Changed
T
PLL(1)
1
2
n-1 n
Clock
OSTS bit Set
Transition
(2)
Multiplexer
T
OST(1)