Texas Instruments Evaluation Kit for FPD-Link Family of Serializer and Deserializer LVDS Devices FLINK3V8BT-85/NOPB FLINK3V8BT-85/NOPB Hoja De Datos
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FLINK3V8BT-85/NOPB
FPD-Link Evaluation Kit User’s Manual
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 14 of 25
Date: 9/25/2007
Page 14 of 25
LVDS Mapping by IDC Connector
The following two figures illustrate how the Rx outputs are mapped to the IDC
connector (J1) (Note
–
labels are also printed on the demo boards). The 20-pin IDC
connector (J2) pinout is also shown.
2
Previous Cycle
Next Cycle
RXIN3
RXIN2
RXIN1
RXIN0
RXCLKIN
60
59
Pin 1
RXOUT27
GND
RXOUT26
GND
RXOUT25
GND
RXOUT24
GND
RXOUT23
GND
RXOUT22
GND
RXOUT21
GND
RXOUT20
GND
RXOUT19
GND
RXOUT18
GND
RXOUT17
GND
RXOUT16
GND
RXOUT15
GND
RXOUT14
GND
RXOUT13
GND
RXOUT12
GND
RXOUT11
GND
RXOUT10
GND
RXOUT9
GND
RXOUT8
GND
RXOUT7
GND
RXOUT6
GND
RXOUT5
GND
RXOUT4
GND
RXOUT3
GND
RXOUT2
GND
RXOUT1
GND
RXOUT0
GND
RXCLKOUT
GND
GND
GND
J1
60-pin IDC Connector
RxIN LVDS signals
20-pin IDC connector
(Receiver Board)
RXIN3
RXIN2
RXIN0
RXIN0
RXIN1
RXIN2
RXIN1
RXIN1
RXOUT23 RXOUT17 RXOUT16 RXOUT11 RXOUT10 RXOUT5 RXOUT27
RXOUT26 RXOUT25 RXOUT24 RXOUT22 RXOUT21 RXOUT20 RXOUT19
RXOUT18 RXOUT15 RXOUT14 RXOUT13 RXOUT12 RXOUT9 RXOUT8
RXOUT7 RXOUT6 RXOUT4 RXOUT3 RXOUT2 RXOUT1 RXOUT0
LVDS Data Inputs Mapped to LVTTL/LVCMOS Outputs
2
Pin 1
20
19
GND
IN0-
IN0+
GND
GND
IN1-
IN1+
GND
GND
IN2-
IN2+
GND
GND
CLK-
CLK+
GND
GND
IN3-
IN3+
GND
J2