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PIC18F65J15-I/PT
PIC18F87J10 FAMILY
DS39663F-page 180
© 2009 Microchip Technology Inc.
TABLE 18-3:
PIN CONFIGURATIONS FOR ECCP3
18.2
Capture and Compare Modes
Except for the operation of the Special Event Trigger
discussed below, the Capture and Compare modes of
the ECCP module are identical in operation to that of
CCP4. These are discussed in detail in Section 17.2
“Capture Mode” and Section 17.3 “Compare
Mode”.
discussed below, the Capture and Compare modes of
the ECCP module are identical in operation to that of
CCP4. These are discussed in detail in Section 17.2
“Capture Mode” and Section 17.3 “Compare
Mode”.
18.2.1
SPECIAL EVENT TRIGGER
ECCP1 and ECCP2 incorporate an internal hardware
trigger that is generated in Compare mode on a match
between the CCPRx register pair and the selected
timer. This can be used in turn to initiate an action. This
mode is selected by setting CCPxCON<3:0> to ‘1011’.
The Special Event Trigger output of either ECCP1 or
ECCP2 resets the TMR1 or TMR3 register pair, depend-
ing on which timer resource is currently selected. This
allows the CCPRx register pair to effectively be a 16-bit
programmable period register for Timer1 or Timer3. In
addition, the ECCP2 Special Event Trigger will also start
an A/D conversion if the A/D module is enabled.
trigger that is generated in Compare mode on a match
between the CCPRx register pair and the selected
timer. This can be used in turn to initiate an action. This
mode is selected by setting CCPxCON<3:0> to ‘1011’.
The Special Event Trigger output of either ECCP1 or
ECCP2 resets the TMR1 or TMR3 register pair, depend-
ing on which timer resource is currently selected. This
allows the CCPRx register pair to effectively be a 16-bit
programmable period register for Timer1 or Timer3. In
addition, the ECCP2 Special Event Trigger will also start
an A/D conversion if the A/D module is enabled.
Special Event Triggers are not implemented for
ECCP3, CCP4 or CCP5. Selecting the Special Event
Trigger mode for these modules has the same effect as
selecting the Compare with Software Interrupt mode
(CCPxM<3:0> = 1010).
ECCP3, CCP4 or CCP5. Selecting the Special Event
Trigger mode for these modules has the same effect as
selecting the Compare with Software Interrupt mode
(CCPxM<3:0> = 1010).
18.3
Standard PWM Mode
When configured in Single Output mode, the ECCP
module functions identically to the standard CCP
module in PWM mode, as described in Section 17.4
“PWM Mode”. This is also sometimes referred to as
“Compatible CCP” mode as in Tables 18-1
through 18-3.
module functions identically to the standard CCP
module in PWM mode, as described in Section 17.4
“PWM Mode”. This is also sometimes referred to as
“Compatible CCP” mode as in Tables 18-1
through 18-3.
ECCP Mode
CCP3CON
Configuration
RG0
RE4
RE3
RG3
RH5
RH4
All PIC18F6XJ10/6XJ15 Devices:
Compatible CCP
00xx 11xx
ECCP3
RE4
RE3
RG3/CCP4
N/A
N/A
Dual PWM
10xx 11xx
P3A
P3B
RE3
RG3/CCP4
N/A
N/A
Quad PWM
x1xx 11xx
P3A
P3B
P3C
P3D
N/A
N/A
PIC18F8XJ10/8XJ15 Devices, ECCPMX = 0, Microcontroller mode:
Compatible CCP
00xx 11xx
ECCP3
RE6/AD14
RE5/AD13
RG3/CCP4
RH7/AN15
RH6/AN14
Dual PWM
10xx 11xx
P3A
RE6/AD14
RE5/AD13
RG3/CCP4
P3B
RH6/AN14
Quad PWM
x1xx 11xx
P3A
RE6/AD14
RE5/AD13
P3D
P3B
P3C
PIC18F8XJ10/8XJ15 Devices, ECCPMX = 1, Extended Microcontroller mode, 16-Bit or 20-Bit Address Width:
Compatible CCP
00xx 11xx
ECCP3
RE6/AD14
RE5/AD13
RG3/CCP4
RH7/AN15
RH6/AN14
PIC18F8XJ10/8XJ15 Devices, ECCPMX = 1,
Microcontroller mode or Extended Microcontroller mode, 12-Bit Address Width:
Compatible CCP
00xx 11xx
ECCP3
RE4/AD12
RE3/AD11
RG3/CCP4
RH5/AN13
RH4/AN12
Dual PWM
10xx 11xx
P3A
P3B
RE3/AD11
RG3/CCP4
RH5/AN13
RH4/AN12
Quad PWM
x1xx 11xx
P3A
P3B
P3C
P3D
RH5/AN13
RH4/AN12
Legend: x = Don’t care, N/A = Not available. Shaded cells indicate pin assignments not used by ECCP3 in a given mode.
Note 1:
Note 1:
With ECCP3 in Quad PWM mode, CCP4’s output is overridden by P1D; otherwise, CCP4 is fully operational.
Note:
The Special Event Trigger from ECCP2
will not set the Timer1 or Timer3 interrupt
flag bits.
will not set the Timer1 or Timer3 interrupt
flag bits.
Note:
When setting up single-output PWM
operations, users are free to use either of
the processes described in Section 17.4.3
“Setup for PWM Operation” or
Section 18.4.9 “Setup for PWM Opera-
tion”. The latter is more generic but will
work for either single or multi-output PWM.
operations, users are free to use either of
the processes described in Section 17.4.3
“Setup for PWM Operation” or
Section 18.4.9 “Setup for PWM Opera-
tion”. The latter is more generic but will
work for either single or multi-output PWM.