Texas Instruments Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.2 GHz VCO LMK04805BEVAL/NOPB LMK04805BEVAL/NOPB Hoja De Datos

Los códigos de productos

LMK04805BEVAL/NOPB

L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S

Table of Contents

TABLE OF CONTENTS .............................................................................................................................................. 2

GENERAL DESCRIPTION .......................................................................................................................................... 4

VALUATION

OARD

ONTENTS

.................................................................................................................................. 4

..................................................................................................................... 4

........................................................................................................................... 4

QUICK START ......................................................................................................................................................... 5

.................................................................................................... 6

EXAMPLE: USING CODELOADER TO PROGRAM THE LMK04808B ........................................................................... 7

.............................................................................................................................. 7

ELECT

EVICE

.......................................................................................................................................................... 7

ROGRAM

OAD

EVICE

............................................................................................................................................. 8

ESTORING A

EFAULT

ODE

...................................................................................................................................... 8

.................................................................................................................. 9

NABLE

LOCK

UTPUTS

............................................................................................................................................. 9

PLL LOOP FILTERS AND LOOP PARAMETERS......................................................................................................... 11

PLL

OOP

ILTER

...................................................................................................................................................... 11

122.88 MHz VCXO PLL ........................................................................................................................................ 11

PLL2

OOP

ILTER

....................................................................................................................................................... 12

Integrated VCO PLL ............................................................................................................................................ 12

EVALUATION BOARD INPUTS AND OUTPUTS ....................................................................................................... 13

RECOMMENDED TEST EQUIPMENT...................................................................................................................... 21

PROGRAMMING 0-DELAY MODE IN CODELOADER .............................................................................................. 22

VERVIEW

.................................................................................................................................................................. 22

........................................................................................................................... 22

Programming Steps ............................................................................................................................................ 22

Details ................................................................................................................................................................ 22

......................................................................................................................... 24

Programming Steps ............................................................................................................................................ 24

Details ................................................................................................................................................................ 24

APPENDIX A: CODELOADER USAGE ...................................................................................................................... 26

ORT

ETUP

......................................................................................................................................................... 26

LOCK

UTPUTS

................................................................................................................................................... 27

PLL1

................................................................................................................................................................... 29

Setting the PLL1 VCO Frequency and PLL2 Reference Frequency ....................................................................... 30

PLL2

................................................................................................................................................................... 31

ITS

INS

............................................................................................................................................................ 32

EGISTERS

............................................................................................................................................................ 37

APPENDIX B: TYPICAL PHASE NOISE PERFORMANCE PLOTS ................................................................................. 38

PLL1 ......................................................................................................................................................................... 38

122.88 MHz VCXO Phase Noise .......................................................................................................................... 38

Clock Output Measurement Technique .............................................................................................................. 39

Buffered OSCout Phase Noise............................................................................................................................. 39