Texas Instruments OPA1S2385 Evaluation Module OPA1S2385EVM OPA1S2385EVM Hoja De Datos
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OPA1S2385EVM
+
+
SC
V–
V+
C1
V
OUT
R1
V
IN
SBOS645A – DECEMBER 2012 – REVISED JUNE 2013
Sample and Hold
The OPA1S238x can be used in a basic sample-and-hold configuration.
shows the simplified circuit for
this application.
Figure 28. Sample-and-Hold Circuit
This sample-and-hold circuit can be used to sample the V
IN
voltage at a specific point in time and hold it at V
OUT
.
This functionality is especially useful when fast-moving signals must be digitized.
When the switch connecting the two op amps is closed, the circuit operates in track mode. In track mode, if ideal
components are assumed, the voltage at V
components are assumed, the voltage at V
OUT
follows the voltage at V
IN
, only delayed by a filter consisting of R1
and C1.
As soon as the internal switch is opened, the output voltage no longer follows the input voltage. If ideal
components are assumed again, the change in C1 remains constant and voltage at V
components are assumed again, the change in C1 remains constant and voltage at V
OUT
reflects the voltage at
V
IN
at the moment that the switch was opened.
The values of R1 and C1 must be chosen depending on the bandwidth of the input signal, the sample time, and
the hold time. Long hold times require larger capacitors in order to reduce the error from any leakage currents
coming out of C1. Short sample times require smaller capacitors to allow for fast settling. It is important to
choose the R1 value according to
the hold time. Long hold times require larger capacitors in order to reduce the error from any leakage currents
coming out of C1. Short sample times require smaller capacitors to allow for fast settling. It is important to
choose the R1 value according to
to prevent ringing or excessive damping, and to include the
influence of switch on resistance in this selection.
There are several error sources that should be considered when designing a sample-and-hold circuit. The most
important ones are:
•
important ones are:
•
Aperture Time is the time required for a switch to open and remove the charging signal from the capacitor
after the mode control signal has changed from sample to hold.
after the mode control signal has changed from sample to hold.
•
Effective Aperture Time is the difference in propagation delay times of the analog signal and the mode
control signal from their respective input pins to the switch.
control signal from their respective input pins to the switch.
•
Charge Offset is the output voltage change that results from a charge transfer into the hold capacitor through
stray capacitance when Hold mode is enabled.
stray capacitance when Hold mode is enabled.
•
Droop Rate is the change in output voltage over time during Hold mode as a result of hold capacitor leakage,
switch leakage, and bias current of the output amplifier.
switch leakage, and bias current of the output amplifier.
•
Drift Current is the net leakage current affecting the hold capacitor during Hold mode.
•
Hold Mode Feedthrough is the fraction of the input signal that appears at the output while in Hold mode. It is
primarily a function of switch capacitance, but may also be increased by poor layout practices.
primarily a function of switch capacitance, but may also be increased by poor layout practices.
•
Hold Mode Settling Time is the time required for the sample-to-hold transient to settle within a specified
error band.
error band.
14
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