Texas Instruments THS7320YHCEVM Evaluation Module THS7320YHCEVM THS7320YHCEVM Hoja De Datos
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THS7320YHCEVM
V
S+
Enable
LPF
3-Pole
20-MHz
2 V/V
2 V/V
Level
Shift
LPF
3-Pole
20-MHz
2 V/V
2 V/V
Level
Shift
LPF
3-Pole
20-MHz
2 V/V
2 V/V
Level
Shift
Channel 1 Input
Channel 1 Output
Channel 2 Input
Channel 2 Output
Channel 3 Input
Channel 3 Output
1 MW
A
2
1
3
B
C
Ch 1 IN
GND
Ch 1 OUT
Ch 2 IN
EN
Ch 2 OUT
Ch 3 IN
V
S+
Ch 3 OUT
SBOS565B – JULY 2011 – REVISED SEPTEMBER 2012
PIN CONFIGURATION
YHC PACKAGE
WCSP 9-BALL
(TOP VIEW)
PIN ASSIGNMENTS
NAME
NO.
I/O
DESCRIPTION
Channel 1 input
A1
I
Video input, channel 1
GND
A2
I
Ground for all circuitry
Channel 1 output
A3
O
Video output, channel 1
Channel 2 input
B1
I
Video input, channel 2
Video enable pin. Logic high enables the video channels; logic low disables the video
EN
B2
I
channels.
Channel 2 output
B3
O
Video output, channel 2
Channel 3 input
C1
I
Video input, channel 3
V
S+
C2
I
Power-supply pin; connect to +2.6 V up to +5 V.
Channel 3 output
C3
O
Video output, channel 3
FUNCTIONAL BLOCK DIAGRAM
6
Copyright © 2011–2012, Texas Instruments Incorporated
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