Texas Instruments LV32EVK01 Evaluation Kit LV32EVK01/NOPB LV32EVK01/NOPB Hoja De Datos
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LV32EVK01/NOPB
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Configuration Settings for the Serializer Board
S1: Serializer Input Features Selection
Reference
Description
Input = L
Input = H
S1
PWDNB
PoWerDowN Bar Powers
Down
Normal
operation
operation
(Default)
BISTEN
BIST ENable BIST
mode
disabled
(Default)
BIST mode
enabled
enabled
TRFB
Latch input data
on Rising or
Falling edge of
TCLK
on Rising or
Falling edge of
TCLK
Falling
Edge
Edge
(Default)
Rising
Edge
Edge
MODE
DB/Q
DB/Q
Dual or Quad
mode
mode
Dual mode
(Default)
Quad mode
RES_0
REServed
MUST be
tied low for
normal
operation
tied low for
normal
operation
(Default)
Not allowed
V SEL
LVDS output V
OD
SELect
≈440 mV
P-P
(Default)
≈850 mV
P-P
JP2: Serializer Input Features Selection
Reference Description
Default External
JP2
IOVDD 1.8V
input
option.
For 1.8V input
swing IOVDD is
connected to
VDDI. VDDI
must be applied
on JP1 pin 1.
For 1.8V input
swing IOVDD is
connected to
VDDI. VDDI
must be applied
on JP1 pin 1.
Connected
to VDD (J7)
to VDD (J7)
National Semiconductor Corporation
Date: 9/28/2009
Page 7 of 34
Page 7 of 34