Texas Instruments SN65LVDS4 Evaluation Module SN65LVDS4EVM SN65LVDS4EVM Hoja De Datos
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SN65LVDS4EVM
Power Supply Configuration
4
Power Supply Configuration
Two power supplies are needed to bias the SN65LVDS4
–
VCC, the core power supply, and VDD, the
output drive power supply. For proper device operation, it is recommended that VCC is powered up first
and then VDD or VCC applied at the same time as VDD (In the later case, VCC and VDD are tied
together). Further, it is also recommended that VCC is equal to or less than VDD as shown in
and then VDD or VCC applied at the same time as VDD (In the later case, VCC and VDD are tied
together). Further, it is also recommended that VCC is equal to or less than VDD as shown in
Table 1. Power Supply Acceptable Combinations
VCC (V)
VDD (V)
Recommended
1.8
1.8
Yes
1.8
2.5
Yes
1.8
3.3
Yes
2.5
1.8
No
2.5
2.5
Yes
2.5
3.3
Yes
5
Test Setup
Measuring the output signal on J2 with a 50-
Ω
cable terminated into 50
Ω
at the scope attenuates the
signal due to the 453-
Ω
resistor (R1) in series with the receiver output on the EVM board. The resistor is
installed as a current limit for termination into a 50-
Ω
load, thus providing a 10x attenuation on the
measured output signal.
Measuring the output signal with a high-impedance probe on JMP1 requires removing R1, the 453-
Ω
resistor, and installing a 0-
Ω
resistor on R4 (0402). Measuring the output signal on JMP1 allows the user
to see absolute signal levels out of the device.
See
for input and output connections.
Table 2. EVM and Device Connections
Pin
EVM Connection
I/O
Description
Name
No.
J1
A
2
I
LVDS input, positive
J3
B
3
I
LVDS input, negative
P2
GND
1, 7
—
Ground
—
NC
4, 6, 9
—
No connect
J2
R
8
O
1.8/2.5 LVCMOS/3.3 LVTTL output
P1
VCC
5
—
Core supply voltage
P3
VDD
10
—
Output supply voltage
3
SLLU151
–
July 2011
SN65LVDS4 Evaluation Module
Copyright
©
2011, Texas Instruments Incorporated