Microchip Technology DV164136 Hoja De Datos
PIC18F8722 FAMILY
DS39646C-page 410
© 2008 Microchip Technology Inc.
FIGURE 28-18:
EXAMPLE SPI SLAVE MODE TIMING (CKE =
1
)
TABLE 28-19: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE =
1
)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
T
SS
L2
SC
H,
T
SS
L2
SC
L
SSx
↓ to SCKx ↓ or SCKx ↑ Input
3 T
CY
—
ns
71
T
SC
H
SCKx Input High Time
(Slave mode)
(Slave mode)
Continuous
1.25 T
CY
+ 30
—
ns
71A
Single Byte
40
—
ns
(Note 1)
72
T
SC
L
SCKx Input Low Time
(Slave mode)
(Slave mode)
Continuous
1.25 T
CY
+ 30
—
ns
72A
Single Byte
40
—
ns
(Note 1)
73A
T
B
2
B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 T
CY
+ 40
—
ns
(Note 2)
74
T
SC
H2
DI
L,
T
SC
L2
DI
L
Hold Time of SDIx Data Input to SCKx Edge
40
—
ns
75
T
DO
R
SDOx Data Output Rise Time
PIC18FXXXX
—
25
ns
PIC18LFXXXX
—
45
ns
V
DD
= 2.0V
76
T
DO
F
SDOx Data Output Fall Time
—
25
ns
77
T
SS
H2
DO
Z SSx
↑ to SDOx Output High-Impedance
10
50
ns
78
T
SC
R
SCKx Output Rise Time
(Master mode)
(Master mode)
PIC18FXXXX
—
25
ns
PIC18LFXXXX
—
45
ns
V
DD
= 2.0V
79
T
SC
F
SCKx Output Fall Time (Master mode)
—
25
ns
80
T
SC
H2
DO
V,
T
SC
L2
DO
V
SDOx Data Output Valid after SCKx
Edge
Edge
PIC18FXXXX
—
50
ns
PIC18LFXXXX
—
100
ns
V
DD
= 2.0V
82
T
SS
L2
DO
V SDOx Data Output Valid after SSx
↓
Edge
PIC18FXXXX
—
50
ns
PIC18LFXXXX
—
100
ns
V
DD
= 2.0V
83
T
SC
H2
SS
H,
T
SC
L2
SS
H
SSx
↑ after SCKx Edge
1.5 T
CY
+ 40
—
ns
Note 1:
Requires the use of Parameter #73A.
2:
Only if Parameter #71A and #72A are used.
SSx
SCKx
(CKP =
(CKP =
0
)
SCKx
(CKP =
(CKP =
1
)
SDOx
SDI
70
71
72
82
SDIx
74
75, 76
MSb
bit 6 - - - - - - 1
LSb
77
MSb In
bit 6 - - - - 1
LSb In
80
83
Note:
Refer to Figure 28-5 for load conditions.