Microchip Technology MA320001 Hoja De Datos

2011 Micr

och

ip T
e

chn

logy Inc.

1143H-p

age 67

PIC32MX3XX/4XX

3260 DCH2DPTR

31:16

—

0000

15:0

—

CHDPTR<7:0>

0000

3270 DCH2CSIZ

31:16

—

0000

15:0

—

CHCSIZ<7:0>

0000

3280 DCH2CPTR

31:16

—

0000

15:0

—

CHCPTR<7:0>

0000

3290

DCH2DAT

31:16

—

0000

15:0

—

CHPDAT<7:0>

0000

32A0 DCH3CON

31:16

—

0000

15:0

—

CHCHNS

CHEN

CHAED

CHCHN

CHAEN

—

CHEDET

CHPRI<1:0>

0000

32B0 DCH3ECON

31:16

—

CHAIRQ<7:0>

00FF

15:0

CHSIRQ<7:0>

CFORCE

CABORT

PATEN

SIRQEN

AIRQEN

—

FF00

32C0

DCH3INT

31:16

—

CHSDIE

CHSHIE

CHDDIE

CHDHIE

CHBCIE

CHCCIE

CHTAIE

CHERIE

0000

15:0

—

CHSDIF

CHSHIF

CHDDIF

CHDHIF

CHBCIF

CHCCIF

CHTAIF

CHERIF

0000

32D0

DCH3SSA

31:16

CHSSA<31:0>

0000

15:0

0000

32E0

DCH3DSA

31:16

CHDSA<31:0>

0000

15:0

0000

32F0 DCH3SSIZ

31:16

—

0000

15:0

—

CHSSIZ<7:0>

0000

3300 DCH3DSIZ

31:16

—

0000

15:0

—

CHDSIZ<7:0>

0000

3310 DCH3SPTR

31:16

—

0000

15:0

—

CHSTR<7:0>

0000

3320 DCH3DPTR

31:16

—

0000

15:0

—

CHDPTR<7:0>

0000

3330 DCH3CSIZ

31:16

—

0000

15:0

—

CHCSIZ<7:0>

0000

3340 DCH3CPTR

31:16

—

0000

15:0

—

CHCPTR<7:0>

0000

3350

DCH3DAT

31:16

—

0000

15:0

—

CHPDAT<7:0>

0000

TABLE 4-16:

DMA CHANNELS 0-3 REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX
DEVICES ONLY

(1)

(CONTINUED)

irtual Addr

8_#)

gist

Name

Bit Range

Bits

ll Re

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

Legend:

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note

All registers except DCHxSPTR, DCHxDPTR and DCHxCPTR have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See

Section 12.1.1 “CLR,

SET and INV Registers”

for more information.