Microchip Technology MA330018 Hoja De Datos
© 2007-2012 Microchip Technology Inc.
DS70291G-page 21
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
3.0
CPU
3.1
Overview
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 CPU module has
a 16-bit (data) modified Harvard architecture with an
enhanced instruction set, including significant support
for DSP. The CPU has a 24-bit instruction word with a
variable length opcode field. The Program Counter
(PC) is 23 bits wide and addresses up to 4M x 24 bits
of user program memory space. The actual amount of
program memory implemented varies by device. A
single-cycle instruction prefetch mechanism is used to
help maintain throughput and provides predictable
execution. All instructions execute in a single cycle,
with the exception of instructions that change the
program flow, the double-word move (MOV.D)
instruction and the table instructions. Overhead-free
program loop constructs are supported using the DO
and REPEAT instructions, both of which are
interruptible at any time.
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 devices have
sixteen, 16-bit working registers in the programmer’s
model. Each of the working registers can serve as a
data, address or address offset register. The 16th
working register (W15) operates as a software Stack
Pointer (SP) for interrupts and calls.
X04 and dsPIC33FJ128MCX02/X04 CPU module has
a 16-bit (data) modified Harvard architecture with an
enhanced instruction set, including significant support
for DSP. The CPU has a 24-bit instruction word with a
variable length opcode field. The Program Counter
(PC) is 23 bits wide and addresses up to 4M x 24 bits
of user program memory space. The actual amount of
program memory implemented varies by device. A
single-cycle instruction prefetch mechanism is used to
help maintain throughput and provides predictable
execution. All instructions execute in a single cycle,
with the exception of instructions that change the
program flow, the double-word move (MOV.D)
instruction and the table instructions. Overhead-free
program loop constructs are supported using the DO
and REPEAT instructions, both of which are
interruptible at any time.
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 devices have
sixteen, 16-bit working registers in the programmer’s
model. Each of the working registers can serve as a
data, address or address offset register. The 16th
working register (W15) operates as a software Stack
Pointer (SP) for interrupts and calls.
There are two classes of instruction in the
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04
and dsPIC33FJ128MCX02/X04 devices: MCU and
DSP. These two instruction classes are seamlessly
integrated into a single CPU. The instruction set
includes many addressing modes and is designed for
optimum C compiler efficiency. For most instructions,
the dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 is capable of
executing a data (or program data) memory read, a
working register (data) read, a data memory write and
a program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.
A block diagram of the CPU is shown in
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04
and dsPIC33FJ128MCX02/X04 devices: MCU and
DSP. These two instruction classes are seamlessly
integrated into a single CPU. The instruction set
includes many addressing modes and is designed for
optimum C compiler efficiency. For most instructions,
the dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 is capable of
executing a data (or program data) memory read, a
working register (data) read, a data memory write and
a program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.
A block diagram of the CPU is shown in
, and
the programmer’s model for the dsPIC33FJ32MC302/
304, dsPIC33FJ64MCX02/X04 and
dsPIC33FJ128MCX02/X04 is shown in
304, dsPIC33FJ64MCX02/X04 and
dsPIC33FJ128MCX02/X04 is shown in
.
3.2
Data Addressing Overview
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through the
X memory AGU, which accesses the entire memory
map as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device-specific.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software
boundary checking overhead for DSP algorithms.
Furthermore, the X AGU circular addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data reordering for radix-2 FFT
algorithms.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space Visibility Page (PSVPAG) register. The
program-to-data-space mapping feature lets any
instruction access program space as if it were data
space.
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through the
X memory AGU, which accesses the entire memory
map as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device-specific.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software
boundary checking overhead for DSP algorithms.
Furthermore, the X AGU circular addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data reordering for radix-2 FFT
algorithms.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space Visibility Page (PSVPAG) register. The
program-to-data-space mapping feature lets any
instruction access program space as if it were data
space.
Note 1: This data sheet summarizes the features
of
dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04 and
dsPIC33FJ128MCX02/X04 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 2. “CPU”
(DS70204) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(
dsPIC33FJ128MCX02/X04 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 2. “CPU”
(DS70204) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(
www.microchip.com
).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
available on all devices. Refer to
in
this data sheet for device-specific register
and bit information.
and bit information.