Microchip Technology ADM00310 Hoja De Datos
© 2011 Microchip Technology Inc.
DS25048B-page 37
MCP3903
7.0
INTERNAL REGISTERS
The addresses associated with the internal registers
are listed below. All registers are 24 bits long and can
be addressed separately. A detailed description of the
registers follows.
are listed below. All registers are 24 bits long and can
be addressed separately. A detailed description of the
registers follows.
.
The following table shows how the internal address
counter will loop on specific register groups and types.
counter will loop on specific register groups and types.
7.1
Channel Output Registers
The ADC Channel data output registers always contain
the most recent A/D conversion data for each channel.
These registers are read-only. They can be accessed
independently or linked together (with READ<1:0>
bits). These registers are latched when an ADC read
communication occurs. When a data ready event
occurs during a read communication, the most current
ADC data is also latched to avoid data corruption
issues. The three bytes of each channel are updated
synchronously at a DRCLK rate. The three bytes can
be accessed separately if needed, but are refreshed
synchronously. The coding is 23-bit + sign two’s
complement (see Section 5.5).
the most recent A/D conversion data for each channel.
These registers are read-only. They can be accessed
independently or linked together (with READ<1:0>
bits). These registers are latched when an ADC read
communication occurs. When a data ready event
occurs during a read communication, the most current
ADC data is also latched to avoid data corruption
issues. The three bytes of each channel are updated
synchronously at a DRCLK rate. The three bytes can
be accessed separately if needed, but are refreshed
synchronously. The coding is 23-bit + sign two’s
complement (see Section 5.5).
TABLE 7-1:
INTERNAL REGISTER SUMMARY
Address
Name
Bits
R/W
Description
0x00
CHANNEL 0
24
R
Channel 0 ADC Data <23:0>, MSB first, left justified
0x01
CHANNEL 1
24
R
Channel 1 ADC Data <23:0>, MSB first, left justified
0x02
CHANNEL 2
24
R
Channel 2 ADC Data <23:0>, MSB first, left justified
0x03
CHANNEL 3
24
R
Channel 3 ADC Data <23:0>, MSB first, left justified
0x04
CHANNEL 4
24
R
Channel 4 ADC Data <23:0>, MSB first, left justified
0x05
CHANNEL 5
24
R
Channel 5 ADC Data <23:0>, MSB first, left justified
0x06
MOD
24
R/W Delta Sigma Modulators Output Value
0x07
PHASE
24
R/W Phase Delay Configuration Register
0x08
GAIN
24
R/W Gain Configuration Register
0x09
STATUS/COM
24
R/W Status/Communication Register
0x0A
CONFIG
24
R/W Configuration Register
TABLE 7-2:
CONTINUOUS READ
OPTIONS, LOOPING ON
INTERNAL ADDRESSES
OPTIONS, LOOPING ON
INTERNAL ADDRESSES
Function
Address
READ<1:0>
= “01”
= “10”
=“11”
CHANNEL 0
0x00
GROUP
TYPE
LO
O
P
E
N
T
IRE REGISTER MAP
CHANNEL 1
0x01
CHANNEL 2
0x02
GROUP
CHANNEL 3
0x03
CHANNEL 4
0x04
GROUP
CHANNEL 5
0x05
MOD
0x06
GRO
U
P
TYPE
PHASE
0x07
GAIN
0x08
STATUS/
COM
0x09
GR
O
U
P
CONFIG
0x0A
TABLE 7-3:
ADC OUTPUT REGISTERS
Name
Bits
Address
Cof
CHANNEL 0
24
0x00
R
CHANNEL 1
24
0x01
R
CHANNEL 2
24
0x02
R
CHANNEL 3
24
0x03
R
CHANNEL 4
24
0x04
R
CHANNEL 5
24
0x05
R