Microchip Technology AC164337 Hoja De Datos
2006-2014 Microchip Technology Inc.
DS70000178D-page 29
dsPIC30F1010/202X
3.0
MEMORY ORGANIZATION
3.1
Program Address Space
The program address space is 4M instruction words. It
is addressable by a 24-bit value from either the 23-bit
PC, table instruction Effective Address (EA), or data
space EA, when program space is mapped into data
space, as defined by Table 3-1. Note that the program
space address is incremented by two between succes-
sive program words, in order to provide compatibility
with data space addressing.
is addressable by a 24-bit value from either the 23-bit
PC, table instruction Effective Address (EA), or data
space EA, when program space is mapped into data
space, as defined by Table 3-1. Note that the program
space address is incremented by two between succes-
sive program words, in order to provide compatibility
with data space addressing.
User program space access is restricted to the lower
4M instruction word address range (0x000000 to
0x7FFFFE), for all accesses other than TBLRD/TBLWT,
which use TBLPAG<7> to determine user or configura-
tion space access. In Table 3-1, Read/Write instruc-
tions, bit 23 allows access to the Device ID, the User ID
and the Configuration bits. Otherwise, bit 23 is always
clear.
4M instruction word address range (0x000000 to
0x7FFFFE), for all accesses other than TBLRD/TBLWT,
which use TBLPAG<7> to determine user or configura-
tion space access. In Table 3-1, Read/Write instruc-
tions, bit 23 allows access to the Device ID, the User ID
and the Configuration bits. Otherwise, bit 23 is always
clear.
FIGURE 3-1:
PROGRAM SPACE
MEMORY MAP FOR
dsPIC30F1010/202X
MEMORY MAP FOR
dsPIC30F1010/202X
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
Note:
The address map shown in Figure 3-1 is
conceptual, and the actual memory con-
figuration may vary across individual
devices depending on available memory.
conceptual, and the actual memory con-
figuration may vary across individual
devices depending on available memory.
Reset – Target Address
U
s
er
Me
mo
ry
Sp
a
c
e
000000
7FFFFE
00007E
Ext. Osc. Fail Trap
000002
000080
User Flash
Program Memory
002000
001FFE
Address Error Trap
Stack Error Trap
Arithmetic Warn. Trap
Reserved
Reserved
Reserved
Reserved
Reserved
Vector 0
Vector 1
Vector 1
Vector 52
Vector 53
Vector 53
(4K instructions)
Reserved
(Read 0’s)
0000FE
000100
000100
000014
Alternate Vector Table
Reset –
GOTO
Instruction
000004
Reserved
Device Configuration
C
onf
ig
ur
ati
o
n M
e
m
o
ry
Sp
a
c
e
800000
F80000
Registers
F8000E
F80010
F80010
DEVID (2)
FEFFFE
FF0000
FFFFFE
FF0000
FFFFFE
Reserved
F7FFFE
8005FE
800600
800600
UNITID (32 instr.)
8005BE
8005C0
8005C0
Reserved
Reserved
Vector Tables