Microchip Technology MA330031-2 Hoja De Datos
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 108
2011-2013 Microchip Technology Inc.
Allocating different Page registers for read and write
access allows the architecture to support data
movement between different pages in data memory.
This is accomplished by setting the DSRPAG register
value to the page from which you want to read, and
configuring the DSWPAG register to the page to which
it needs to be written. Data can also be moved from
different PSV to EDS pages, by configuring the
DSRPAG and DSWPAG registers to address PSV and
EDS space, respectively. The data can be moved
between pages by a single instruction.
When an EDS or PSV page overflow or underflow
occurs, EA<15> is cleared as a result of the register
indirect EA calculation. An overflow or underflow of the
EA in the EDS or PSV pages can occur at the page
boundaries when:
• The initial address prior to modification addresses
access allows the architecture to support data
movement between different pages in data memory.
This is accomplished by setting the DSRPAG register
value to the page from which you want to read, and
configuring the DSWPAG register to the page to which
it needs to be written. Data can also be moved from
different PSV to EDS pages, by configuring the
DSRPAG and DSWPAG registers to address PSV and
EDS space, respectively. The data can be moved
between pages by a single instruction.
When an EDS or PSV page overflow or underflow
occurs, EA<15> is cleared as a result of the register
indirect EA calculation. An overflow or underflow of the
EA in the EDS or PSV pages can occur at the page
boundaries when:
• The initial address prior to modification addresses
an EDS or PSV page
• The EA calculation uses Pre-Modified or
Post-Modified Register Indirect Addressing;
however, this does not include Register Offset
Addressing
however, this does not include Register Offset
Addressing
In general, when an overflow is detected, the DSxPAG
register is incremented and the EA<15> bit is set to
keep the base address within the EDS or PSV window.
When an underflow is detected, the DSxPAG register is
decremented and the EA<15> bit is set to keep the
base address within the EDS or PSV window. This
creates a linear EDS and PSV address space, but only
when using Register Indirect Addressing modes.
Exceptions to the operation described above arise
when entering and exiting the boundaries of Page 0,
EDS and PSV spaces.
register is incremented and the EA<15> bit is set to
keep the base address within the EDS or PSV window.
When an underflow is detected, the DSxPAG register is
decremented and the EA<15> bit is set to keep the
base address within the EDS or PSV window. This
creates a linear EDS and PSV address space, but only
when using Register Indirect Addressing modes.
Exceptions to the operation described above arise
when entering and exiting the boundaries of Page 0,
EDS and PSV spaces.
lists the effects of
overflow and underflow scenarios at different
boundaries.
In the following cases, when overflow or underflow
occurs, the EA<15> bit is set and the DSxPAG is not
modified; therefore, the EA will wrap to the beginning of
the current page:
• Register Indirect with Register Offset Addressing
• Modulo Addressing
• Bit-Reversed Addressing
boundaries.
In the following cases, when overflow or underflow
occurs, the EA<15> bit is set and the DSxPAG is not
modified; therefore, the EA will wrap to the beginning of
the current page:
• Register Indirect with Register Offset Addressing
• Modulo Addressing
• Bit-Reversed Addressing
TABLE 4-61:
OVERFLOW AND UNDERFLOW SCENARIOS AT PAGE 0, EDS and
PSV SPACE BOUNDARIES
PSV SPACE BOUNDARIES
,
)
O/U,
R/W
Operation
Before
After
DSxPAG
DS
EA<15>
Page
Description
DSxPAG
DS
EA<15>
Page
Description
O,
Read
Read
[++Wn]
or
[Wn++]
DSRPAG = 0x1FF
1
EDS: Last page
DSRPAG = 0x1FF
0
See Note
O,
Read
Read
DSRPAG = 0x2FF
1
PSV: Last lsw
page
page
DSRPAG = 0x300
1
PSV: First MSB
page
page
O,
Read
Read
DSRPAG = 0x3FF
1
PSV: Last MSB
page
page
DSRPAG = 0x3FF
0
See Note
O,
Write
Write
DSWPAG = 0x1FF
1
EDS: Last page
DSWPAG = 0x1FF
0
See Note
U,
Read
Read
[--Wn]
or
[Wn--]
DSRPAG = 0x001
1
PSV page
DSRPAG = 0x001
0
See Note
U,
Read
Read
DSRPAG = 0x200
1
PSV: First lsw
page
page
DSRPAG = 0x200
0
See Note
U,
Read
Read
DSRPAG = 0x300
1
PSV: First MSB
page
page
DSRPAG = 0x2FF
1
PSV: Last lsw
page
page
Legend:
O = Overflow, U = Underflow, R = Read, W = Write
Note 1:
The Register Indirect Addressing now addresses a location in the base Data Space (0x0000-0x8000).
2:
An EDS access with DSxPAG = 0x000 will generate an address error trap.
3:
Only reads from PS are supported using DSRPAG. An attempt to write to PS using DSWPAG will generate
an address error trap.
an address error trap.
4:
Pseudo-Linear Addressing is not supported for large offsets.