Microchip Technology MA330031-2 Hoja De Datos
2011-2013 Microchip Technology Inc.
DS70000657H-page 173
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
11.0
I/O PORTS
Many of the device pins are shared among the peripher-
als and the parallel I/O ports. All I/O input ports feature
Schmitt Trigger inputs for improved noise immunity.
als and the parallel I/O ports. All I/O input ports feature
Schmitt Trigger inputs for improved noise immunity.
11.1
Parallel I/O (PIO) Ports
Generally, a parallel I/O port that shares a pin with a
peripheral is subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
peripheral is subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pin. The logic also prevents “loop through,” in
which a port’s digital output can drive the input of a
peripheral that shares the same pin.
the I/O pin. The logic also prevents “loop through,” in
which a port’s digital output can drive the input of a
peripheral that shares the same pin.
illustrates how ports are shared with other peripherals
and the associated I/O pin to which they are connected.
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as a
general purpose output pin is disabled. The I/O pin can
be read, but the output driver for the parallel port bit is
disabled. If a peripheral is enabled, but the peripheral is
not actively driving a pin, that pin can be driven by a port.
All port pins have eight registers directly associated with
their operation as digital I/O. The Data Direction register
(TRISx) determines whether the pin is an input or an out-
put. If the data direction bit is a ‘1’, then the pin is an input.
All port pins are defined as inputs after a Reset. Reads
from the Latch register (LATx) read the latch. Writes to the
Latch write the latch. Reads from the port (PORTx) read
the port pins, while writes to the port pins write the latch.
Any bit and its associated data and control registers
that are not valid for a particular device is disabled.
This means the corresponding LATx and TRISx
registers and the port pin are read as zeros.
When a pin is shared with another peripheral or
function that is defined as an input only, it is
nevertheless regarded as a dedicated port because
there is no other competing source of outputs.
and the associated I/O pin to which they are connected.
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as a
general purpose output pin is disabled. The I/O pin can
be read, but the output driver for the parallel port bit is
disabled. If a peripheral is enabled, but the peripheral is
not actively driving a pin, that pin can be driven by a port.
All port pins have eight registers directly associated with
their operation as digital I/O. The Data Direction register
(TRISx) determines whether the pin is an input or an out-
put. If the data direction bit is a ‘1’, then the pin is an input.
All port pins are defined as inputs after a Reset. Reads
from the Latch register (LATx) read the latch. Writes to the
Latch write the latch. Reads from the port (PORTx) read
the port pins, while writes to the port pins write the latch.
Any bit and its associated data and control registers
that are not valid for a particular device is disabled.
This means the corresponding LATx and TRISx
registers and the port pin are read as zeros.
When a pin is shared with another peripheral or
function that is defined as an input only, it is
nevertheless regarded as a dedicated port because
there is no other competing source of outputs.
FIGURE 11-1:
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Note 1:
This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
“I/O Ports”
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
“I/O Ports”
(DS70598) in the “dsPIC33/
PIC24 Family Reference Manual
”, which
www.microchip.com
).
2:
Some registers and associated bits
described in this section may not be
available on all devices. Refer to
described in this section may not be
available on all devices. Refer to
in
this data sheet for device-specific register
and bit information.
and bit information.
Q
D
CK
WR LAT +
TRIS Latch
I/O Pin
WR Port
Data Bus
Q
D
CK
Data Latch
Read Port
Read TRIS
1
0
1
0
WR TRIS
Peripheral Output Data
Output Enable
Peripheral Input Data
I/O
Peripheral Module
Peripheral Output Enable
PIO Module
Output Multiplexers
Output Data
Input Data
Peripheral Module Enable
Read LAT