Microchip Technology ARD00385 Hoja De Datos
2009-2011 Microchip Technology Inc.
DS39957D-page 147
PIC18F87K90 FAMILY
REGISTER 10-18: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
R/W-1
R/W-1
R-1
R-1
R/W-1
R/W-1
R/W-1
R/W-1
TMR5GIP
LCDIP
RC2IP
TX2IP
CTMUIP
CCP2IP
CCP1IP
RTCCIP
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
TMR5GIP:
Timer5 Gate interrupt Priority bit
1
= High priority
0
= Low priority
bit 6
LCDIP:
LCD Interrupt Priority bit (valid when the Type-B waveform with Non-Static mode is selected)
1
= High priority
0
= Low priority
bit 5
RC2IP:
AUSART Receive Priority Flag bit
1
= High priority
0
= Low priority
bit 4
TX2IP:
AUSART Transmit Interrupt Priority bit
1
= High priority
0
= Low priority
bit 3
CTMUIP:
CTMU Interrupt Priority bit
1
= High priority
0
= Low priority
bit
CCP2IP:
ECCP2 Interrupt Priority bit
1
= High priority
0
= Low priority
bit
CCP1IP:
ECCP1 Interrupt Priority bit
1
= High priority
0
= Low priority
bit 0
RTCCIP:
RTCC Interrupt Priority bit
1
= High priority
0
= Low priority
REGISTER 10-19: IPR4: PERIPHERAL INTERRUPT PRIORITY REGISTER 4
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
CCP10IP
(
)
CCP9IP
CCP8IP
CCP7IP
CCP6IP
CCP5IP
CCP4IP
CCP3IP
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
CCP10IP:CCP3IP:
CCP<10:3> Interrupt Priority bits
1
= High priority
0
= Low priority
Note 1:
CCP10IP and CCP9IP are unimplemented in devices with a program memory of 32 Kbytes (PIC18FX5K90).