Microchip Technology ARD00385 Hoja De Datos

DS39957D-page 440

 2009-2011 Microchip Technology Inc.

For the PIC18F87K90 family of devices, the WDT is
driven by the LF-INTOSC source. When the WDT is
enabled, the clock source is also enabled. The nominal
WDT period is 4 ms and has the same stability as the
LF-INTOSC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in
Configuration Register 2H. Available periods range
from 4 ms to 4,194 seconds (about one hour). The
WDT and postscaler are cleared when any of the
following events occur: a SLEEP or CLRWDT instruction
is executed, the IRCF bits (OSCCON<6:4>) are
changed or a clock failure has occurred.

The WDT can be operated in one of four modes as
determined by the CONFIG2H bits (WDTEN<1:0>) The
four modes are:
• WDT  Enabled
• WDT Disabled
• WDT under Software Control (WDTCON<0>, 

SWDTEN)

• WDT

- Enabled during normal operation
- Disabled during Sleep

 

 

The  CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.

Changing the setting of the IRCF bits
(OSCCON<6:4>) clears the WDT and
postscaler counts.

When a CLRWDT instruction is executed,
the postscaler count will be cleared.

INTRC Source

WDT 

Reset

 WDT Counter

Programmable Postscaler

1:1 to 1:1,048,576

Enable WDT

WDTPS<3:0>

CLRWDT

4

Reset

All Device Resets

Sleep

128

Change on IRCF<2:0> bits

INTRC Source

Enable WDT

SWDTEN

WDTEN<1:0>

WDT Enabled,

SWDTEN Disabled

WDT Controlled with

SWDTEN bit Setting

WDT Disabled in Hardware,

SWDTEN Disabled

WDT Enabled only While

Device Active, Disabled

WDTEN1

WDTEN0

Wake-up from
Power-Managed
Modes