Microchip Technology MA330019 Hoja De Datos
© 2007-2012 Microchip Technology Inc.
DS70291G-page 327
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
27.0 PARALLEL MASTER PORT
(PMP)
The Parallel Master Port (PMP) module is a parallel
8-bit I/O module, specifically designed to
communicate with a wide variety of parallel devices,
such as communication peripherals, LCDs, external
memory devices and microcontrollers. Because the
interface to parallel peripherals varies significantly,
the PMP is highly configurable.
8-bit I/O module, specifically designed to
communicate with a wide variety of parallel devices,
such as communication peripherals, LCDs, external
memory devices and microcontrollers. Because the
interface to parallel peripherals varies significantly,
the PMP is highly configurable.
Key features of the PMP module include:
• Fully Multiplexed Address/Data Mode
• Fully Multiplexed Address/Data Mode
- 16 bits of address
• Demultiplexed or Partially Multiplexed Address/
Data mode:
- Up to 11 address lines with single Chip Select
- Up to 12 address lines without Chip Select
- Up to 11 address lines with single Chip Select
- Up to 12 address lines without Chip Select
• One Chip Select Line
• Programmable Strobe Options:
• Programmable Strobe Options:
- Individual Read and Write Strobes or;
- Read/Write Strobe with Enable Strobe
- Read/Write Strobe with Enable Strobe
• Address Auto-Increment/Auto-Decrement
• Programmable Address/Data Multiplexing
• Programmable Polarity on Control Signals
• Legacy Parallel Slave Port Support
• Enhanced Parallel Slave Support:
• Programmable Address/Data Multiplexing
• Programmable Polarity on Control Signals
• Legacy Parallel Slave Port Support
• Enhanced Parallel Slave Support:
- Address Support
- 4-Byte Deep Auto-Incrementing Buffer
- 4-Byte Deep Auto-Incrementing Buffer
• Programmable Wait States
• Selectable Input Voltage Levels
• Selectable Input Voltage Levels
FIGURE 27-1:
PMP MODULE OVERVIEW
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04 and
dsPIC33FJ128MCX02/X04 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 35. “Parallel
Master Port (PMP)” (DS70299) of the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip web site
(
dsPIC33FJ64MCX02/X04 and
dsPIC33FJ128MCX02/X04 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 35. “Parallel
Master Port (PMP)” (DS70299) of the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip web site
(
www.microchip.com
).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
available on all devices. Refer to
in
this data sheet for device-specific register
and bit information.
and bit information.
PMA<0>
PMBE
PMRD
PMWR
PMD<7:0>
PMENB
PMRD/PMWR
PMCS1
PMA<1>
PMA<10:2>
PMALL
PMALH
PMA<7:0>
PMA<10:8>
PMA<10:8>
EEPROM
Address Bus
Data Bus
Control Lines
Data Bus
Control Lines
dsPIC33F
LCD
FIFO
Microcontroller
8-bit Data
Up to 11-bit Address
Parallel Master Port
Buffer
Note 1: 28-pin devices do not have PMA<10:2>.
(1)
PMA<14>