Microchip Technology MA330027 Hoja De Datos
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS70616G-page 290
2009-2012 Microchip Technology Inc.
bit 2-0
OCM<2:0>: Output Compare Mode Select bits
111 = Center-Aligned PWM mode: Output set high when OCxTMR = OCxR and set low when
111 = Center-Aligned PWM mode: Output set high when OCxTMR = OCxR and set low when
OCxTMR = OCxRS
110 = Edge-Aligned PWM mode: Output set high when OCxTMR = 0 and set low when
OCxTMR = OCxR
(
)
101 = Double Compare Continuous Pulse mode: Initializes OCx pin low, toggles OCx state continuously
on alternate matches of OCxR and OCxRS
100 = Double Compare Single-Shot mode: Initializes OCx pin low, toggles OCx state on matches of
OCxR and OCxRS for one cycle
011 = Single Compare mode: Compares events with OCxR, continuously toggles OCx pin
010 = Single Compare Single-Shot mode: Initializes OCx pin high, compares event with OCxR, forces
010 = Single Compare Single-Shot mode: Initializes OCx pin high, compares event with OCxR, forces
OCx pin low
001 = Single Compare Single-Shot mode: Initializes OCx pin low, compares event with OCxR, forces
OCx pin high
000 = Output compare channel is disabled
REGISTER 15-1:
OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED)
Note 1: OCxR and OCxRS are double-buffered in PWM mode only.