Microchip Technology MA330011 Hoja De Datos
dsPIC33F
DS70165E-page 342
Preliminary
©
2007 Microchip Technology Inc.
TABLE 26-38: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature
(unless otherwise stated)
Operating temperature
-40°C
≤
T
A
≤
+85°C
Param
No.
Symbol
Characteristic
(1,2)
Min
Typ
(3)
Max
Units
Conditions
CS60
T
BCLKL
BIT_CLK Low Time
36
40.7
45
ns
—
CS61
T
BCLKH
BIT_CLK High Time
36
40.7
45
ns
—
CS62
T
BCLK
BIT_CLK Period
—
81.4
—
ns
Bit clock is input
CS65
T
SACL
Input Setup Time to
Falling Edge of BIT_CLK
Falling Edge of BIT_CLK
—
—
10
ns
—
CS66
T
HACL
Input Hold Time from
Falling Edge of BIT_CLK
Falling Edge of BIT_CLK
—
—
10
ns
—
CS70
T
SYNCLO
SYNC Data Output Low Time
—
19.5
—
μ
s
Note 1
CS71
T
SYNCHI
SYNC Data Output High Time
—
1.3
—
μ
s
Note 1
CS72
T
SYNC
SYNC Data Output Period
—
20.8
—
μ
s
Note 1
CS75
T
RACL
Rise Time, SYNC,
SDATA_OUT
SDATA_OUT
—
10
25
ns
C
LOAD
= 50 pF, V
DD
= 5V
CS76
T
FACL
Fall Time, SYNC, SDATA_OUT
—
10
25
ns
C
LOAD
= 50 pF, V
DD
= 5V
CS77
T
RACL
Rise Time, SYNC,
SDATA_OUT
SDATA_OUT
—
TBD
TBD
ns
C
LOAD
= 50 pF, V
DD
= 3V
CS78
T
FACL
Fall Time, SYNC, SDATA_OUT
—
TBD
TBD
ns
C
LOAD
= 50 pF, V
DD
= 3V
CS80
T
OVDACL
Output Valid Delay from Rising
Edge of BIT_CLK
Edge of BIT_CLK
—
—
15
ns
—
Legend: TBD = To Be Determined
Note 1:
These parameters are characterized but not tested in manufacturing.
2:
These values assume BIT_CLK frequency is 12.288 MHz.
3:
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
are not tested.