Microchip Technology DM164134 Hoja De Datos
© 2006 Microchip Technology Inc.
DS41159E-page 25
PIC18FXX8
3.0
RESET
The PIC18FXX8 differentiates between various kinds
of RESET:
of RESET:
a)
Power-on Reset (POR)
b)
MCLR Reset during normal operation
c)
MCLR Reset during Sleep
d)
Watchdog Timer (WDT) Reset during normal
operation
operation
e)
Programmable Brown-out Reset (PBOR)
f)
RESET
Instruction
g)
Stack Full Reset
h)
Stack Underflow Reset
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset”
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset”
state on Power-on Reset, MCLR, WDT Reset, Brown-
out Reset, MCLR Reset during Sleep and by the
RESET
out Reset, MCLR Reset during Sleep and by the
RESET
instruction.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
POR and BOR are set or cleared differently in different
Reset situations, as indicated in Table 3-2. These bits
are used in software to determine the nature of the
Reset. See Table 3-3 for a full description of the Reset
states of all registers.
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
POR and BOR are set or cleared differently in different
Reset situations, as indicated in Table 3-2. These bits
are used in software to determine the nature of the
Reset. See Table 3-3 for a full description of the Reset
states of all registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 3-1.
is shown in Figure 3-1.
The Enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses.
in the MCLR Reset path. The filter will detect and
ignore small pulses.
A WDT Reset
does not drive MCLR pin low.
FIGURE 3-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
R
Q
External Reset
MCLR
V
DD
OSC1
V
DD
Rise
Detect
OST/PWRT
On-chip
RC OSC
(1)
WDT
Time-out
Power-on Reset
OST
10-bit Ripple Counter
PWRT
Chip_Reset
10-bit Ripple Counter
Reset
Enable OST
(2)
Enable PWRT
Sleep
Note
1:
This is a separate oscillator from the RC oscillator of the CLKI pin.
2: See Table 3-1 for time-out situations.
Brown-out
Reset
BOREN
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
WDT
Module