Microchip Technology DM164134 Hoja De Datos

PIC18FXX8

DS41159E-page 396

Timer1 Oscillator................................................. 21

USART Asynchronous Reception ............................. 192
USART Asynchronous Transmission........................ 190
USART Asynchronous Transmission

(Back to Back)................................................... 190

USART Synchronous Receive

(Master/Slave)................................................... 357

USART Synchronous Reception

(Master Mode, SREN)....................................... 195

USART Synchronous Transmission ......................... 194
USART Synchronous Transmission

(Master/Slave)................................................... 357

USART Synchronous Transmission

(Through TXEN)................................................ 194

Wake-up from Sleep via Interrupt ............................. 275

Timing Diagrams and Specifications................................. 343

A/D Conversion Requirements ................................. 359
A/D Converter Characteristics .................................. 358
Capture/Compare/PWM Requirements

(CCP1 and ECCP1) .......................................... 347

CLKO and I/O Timing

Requirements.................................................... 344

Example SPI Mode Requirements

(Master Mode, CKE = 0) ................................... 349

Example SPI Mode Requirements

(Master Mode, CKE = 1) ................................... 350

Example SPI Mode Requirements

(Slave Mode, CKE = 0) ..................................... 351

Example SPI Slave Mode

Requirements (CKE = 1)................................... 352

External Clock Timing Requirements........................ 343
I

C Bus Data Requirements

(Slave Mode)..................................................... 354

C Bus Start/Stop Bits Requirements

(Slave Mode)..................................................... 353

Master SSP I

C Bus Data

Requirements.................................................... 356

Master SSP I

C Bus Start/Stop Bits

Requirements.................................................... 355

Parallel Slave Port Requirements

(PIC18F248 and PIC18F458) ........................... 348

PLL Clock.................................................................. 344
Reset, Watchdog Timer, Oscillator

Start-up Timer, Power-up Timer,
Brown-out Reset and Low-Voltage
Detect Requirements ........................................ 345

Timer0 and Timer1 External

Clock Requirements.......................................... 346

USART Synchronous Receive

Requirements.................................................... 357

USART Synchronous Transmission

Requirements.................................................... 357

TSTFSZ............................................................................. 321
TXSTA Register

BRGH Bit .................................................................. 185

USART.............................................................................. 183

Asynchronous Mode ................................................. 189

Reception ......................................................... 191
Setting Up 9-Bit Mode with

Address Detect ......................................... 191

Transmission .................................................... 189

Asynchronous Reception.......................................... 192
Asynchronous Transmission

Associated Registers........................................ 190

Baud Rate Generator (BRG) .................................... 185

Associated Registers........................................ 185
Baud Rate Error, Calculating ............................ 185
Baud Rate Formula .......................................... 185
Baud Rates for Asynchronous Mode

(BRGH = 0)............................................... 187

Baud Rates for Asynchronous Mode

(BRGH = 1)............................................... 188

Baud Rates for Synchronous Mode.................. 186
High Baud Rate Select (BRGH Bit) .................. 185
Sampling........................................................... 185

Serial Port Enable (SPEN) Bit .................................. 183
Synchronous Master Mode....................................... 193

Reception ......................................................... 195
Transmission .................................................... 193

Synchronous Master Reception

Associated Registers........................................ 195

Synchronous Master Transmission

Associated Registers........................................ 193

Synchronous Slave Mode......................................... 196

Reception ......................................................... 196
Transmission .................................................... 196

Synchronous Slave Reception.................................. 197
Synchronous Slave Transmission

Associated Registers........................................ 197

Voltage Reference Specifications..................................... 340

Wake-up from Sleep ................................................. 265, 274

Using Interrupts ........................................................ 274

Watchdog Timer (WDT)............................................ 265, 272

Associated Registers ................................................ 273
Control Register........................................................ 272
Postscaler ................................................................. 273
Programming Considerations ................................... 272
RC Oscillator............................................................. 272
Time-out Period ........................................................ 272

WCOL ....................................................... 171, 172 , 173, 176
WCOL Status Flag .................................... 171, 172 , 173, 176
WDT.

See

Watchdog Timer.

WWW, On-Line Support ....................................................... 5

XORLW............................................................................. 321
XORWF ............................................................................ 322