Microchip Technology MA160014 Hoja De Datos
2010-2012 Microchip Technology Inc.
DS41412F-page 127
PIC18(L)F2X/4XK22
REGISTER 9-12:
PIE4: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 4
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
CCP5IE
CCP4IE
CCP3IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-3
Unimplemented: Read as ‘0’
bit 2
CCP5IE: CCP5 Interrupt Enable bit
1
= Enabled
0
= Disabled
bit 1
CCP4IE: CCP4 Interrupt Enable bit
1
= Enabled
0
= Disabled
bit 0
CCP3IE: CCP3 Interrupt Enable bit
1
= Enabled
0
= Disabled
REGISTER 9-13:
PIE5: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 5
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
TMR6IE
TMR5IE
TMR4IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-3
Unimplemented: Read as ‘0’
bit 2
TMR6IE: TMR6 to PR6 Match Interrupt Enable bit
1
= Enables the TMR6 to PR6 match interrupt
0
= Disables the TMR6 to PR6 match interrupt
bit 1
TMR5IE: TMR5 Overflow Interrupt Enable bit
1
= Enables the TMR5 overflow interrupt
0
= Disables the TMR5 overflow interrupt
bit 0
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1
= Enables the TMR4 to PR4 match interrupt
0
= Disables the TMR4 to PR4 match interrupt