Microchip Technology MA160014 Hoja De Datos
2010-2012 Microchip Technology Inc.
DS41412F-page 259
PIC18(L)F2X/4XK22
15.8
Register Definitions: MSSP Control
REGISTER 15-1:
SSPxSTAT: SSPx STATUS REGISTER
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
P
S
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
SMP: SPI Data Input Sample bit
SPI Master mode:
1
1
= Input data sampled at end of data output time
0
= Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
SMP must be cleared when SPI is used in Slave mode
In I
2
C Master or Slave mode:
1
= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0
= Slew rate control enabled for high speed mode (400 kHz)
bit 6
CKE: SPI Clock Edge Select bit (SPI mode only)
In SPI Master or Slave mode:
1
1
= Transmit occurs on transition from active to Idle clock state
0
= Transmit occurs on transition from Idle to active clock state
In I
2
C mode only:
1
= Enable input logic so that thresholds are compliant with SMbus specification
0
= Disable SMbus specific inputs
bit 5
D/A: Data/Address bit (I
2
C mode only)
1
= Indicates that the last byte received or transmitted was data
0
= Indicates that the last byte received or transmitted was address
bit 4
P: Stop bit
(I
2
C mode only. This bit is cleared when the MSSPx module is disabled, SSPxEN is cleared.)
1
= Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0
= Stop bit was not detected last
bit 3
S: Start bit
(I
2
C mode only. This bit is cleared when the MSSPx module is disabled, SSPxEN is cleared.)
1
= Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0
= Start bit was not detected last
bit 2
R/W: Read/Write bit information (I
2
C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match
to the next Start bit, Stop bit, or not ACK bit.
In I
to the next Start bit, Stop bit, or not ACK bit.
In I
2
C Slave mode:
1
= Read
0
= Write
In I
2
C Master mode:
1
= Transmit is in progress
0
= Transmit is not in progress
OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Idle mode.
bit 1
UA: Update Address bit (10-bit I
2
C mode only)
1
= Indicates that the user needs to update the address in the SSPxADD register
0
= Address does not need to be updated
bit 0
BF: Buffer Full Status bit
Receive (SPI and I
2
C modes):
1
= Receive complete, SSPxBUF is full
0
= Receive not complete, SSPxBUF is empty
Transmit (I
2
C mode only):
1
= Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full
0
= Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty