Microchip Technology MA160014 Hoja De Datos
PIC18(L)F2X/4XK22
DS41412E-page 44
2010-2012 Microchip Technology Inc.
2.13
Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue operating should the external oscillator fail.
The FSCM can detect oscillator failure any time after
the Oscillator Start-up Timer (OST) has expired. The
FSCM is enabled by setting the FCMEN bit in the
CONFIG1H Configuration register. The FSCM is
applicable to all external oscillator modes (LP, XT, HS,
EC, RC and RCIO).
to continue operating should the external oscillator fail.
The FSCM can detect oscillator failure any time after
the Oscillator Start-up Timer (OST) has expired. The
FSCM is enabled by setting the FCMEN bit in the
CONFIG1H Configuration register. The FSCM is
applicable to all external oscillator modes (LP, XT, HS,
EC, RC and RCIO).
FIGURE 2-10:
FSCM BLOCK DIAGRAM
2.13.1
FAIL-SAFE DETECTION
The FSCM module detects a failed oscillator by
comparing the external oscillator to the FSCM sample
clock. The sample clock is generated by dividing the
LFINTOSC by 64 (see
comparing the external oscillator to the FSCM sample
clock. The sample clock is generated by dividing the
LFINTOSC by 64 (see
). Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire half-
cycle of the sample clock elapses before the primary
clock goes low.
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire half-
cycle of the sample clock elapses before the primary
clock goes low.
2.13.2
FAIL-SAFE OPERATION
When the external clock fails, the FSCM switches the
device clock to an internal clock source and sets the bit
flag OSCFIF of the PIR2 register. The OSCFIF flag will
generate an interrupt if the OSCFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation. An automatic
transition back to the failed clock source will not occur.
device clock to an internal clock source and sets the bit
flag OSCFIF of the PIR2 register. The OSCFIF flag will
generate an interrupt if the OSCFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation. An automatic
transition back to the failed clock source will not occur.
The internal clock source chosen by the FSCM is
determined by the IRCF<2:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.
determined by the IRCF<2:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.
2.13.3
FAIL-SAFE CONDITION CLEARING
The Fail-Safe condition is cleared by either one of the
following:
following:
• Any Reset
• By toggling the SCS1 bit of the OSCCON register
Both of these conditions restart the OST. While the
OST is running, the device continues to operate from
the INTOSC selected in OSCCON. When the OST
times out, the Fail-Safe condition is cleared and the
device automatically switches over to the external clock
source. The Fail-Safe condition need not be cleared
before the OSCFIF flag is cleared.
OST is running, the device continues to operate from
the INTOSC selected in OSCCON. When the OST
times out, the Fail-Safe condition is cleared and the
device automatically switches over to the external clock
source. The Fail-Safe condition need not be cleared
before the OSCFIF flag is cleared.
2.13.4
RESET OR WAKE-UP FROM SLEEP
The FSCM is designed to detect an oscillator failure
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used with the EC or
RC Clock modes so that the FSCM will be active as
soon as the Reset or wake-up has completed. .
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used with the EC or
RC Clock modes so that the FSCM will be active as
soon as the Reset or wake-up has completed. .
External
LFINTOSC
÷ 64
S
R
Q
31 kHz
(~32
s)
488 Hz
(~2 ms)
Clock Monitor
Latch
Clock
Failure
Detected
Oscillator
Clock
Q
Sample Clock
Note:
Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
OSTS bit of the OSCCON register to verify
the oscillator start-up and that the system
clock switchover has successfully
completed.
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
OSTS bit of the OSCCON register to verify
the oscillator start-up and that the system
clock switchover has successfully
completed.
Note:
When the device is configured for Fail-
Safe clock monitoring in either HS, XT, or
LS Oscillator modes then the IESO config-
uration bit should also be set so that the
clock will automatically switch from the
internal clock to the external oscillator
when the OST times out.
Safe clock monitoring in either HS, XT, or
LS Oscillator modes then the IESO config-
uration bit should also be set so that the
clock will automatically switch from the
internal clock to the external oscillator
when the OST times out.