Microchip Technology MA160014 Hoja De Datos
PIC18(L)F2X/4XK22
DS41412F-page 52
2010-2012 Microchip Technology Inc.
FIGURE 3-5:
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
3.4.1
PRI_IDLE MODE
This mode is unique among the three low-power Idle
modes, in that it does not disable the primary device
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm-up” or transition from another
oscillator.
modes, in that it does not disable the primary device
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm-up” or transition from another
oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruc-
tion. If the device is in another Run mode, set IDLEN
first, then clear the SCS bits and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC<3:0> Configuration bits. The OSTS bit
remains set (see
setting the IDLEN bit and executing a SLEEP instruc-
tion. If the device is in another Run mode, set IDLEN
first, then clear the SCS bits and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC<3:0> Configuration bits. The OSTS bit
remains set (see
).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval T
primary clock source. A delay of interval T
CSD
is
required between the wake event and when code
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the wake-
up, the OSTS bit remains set. The IDLEN and SCS bits
are not affected by the wake-up (see
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the wake-
up, the OSTS bit remains set. The IDLEN and SCS bits
are not affected by the wake-up (see
).
3.4.2
SEC_IDLE MODE
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the SOSC
oscillator. This mode is entered from SEC_RUN by set-
ting the IDLEN bit and executing a SLEEP instruction. If
the device is in another Run mode, set the IDLEN bit
first, then set the SCS<1:0> bits to ‘01’ and execute
SLEEP
peripherals continue to be clocked from the SOSC
oscillator. This mode is entered from SEC_RUN by set-
ting the IDLEN bit and executing a SLEEP instruction. If
the device is in another Run mode, set the IDLEN bit
first, then set the SCS<1:0> bits to ‘01’ and execute
SLEEP
. When the clock source is switched to the SOSC
oscillator, the primary oscillator is shut down, the OSTS
bit is cleared and the SOSCRUN bit is set.
bit is cleared and the SOSCRUN bit is set.
When a wake event occurs, the peripherals continue to
be clocked from the SOSC oscillator. After an interval
of T
be clocked from the SOSC oscillator. After an interval
of T
CSD
following the wake event, the CPU begins exe-
cuting code being clocked by the SOSC oscillator. The
IDLEN and SCS bits are not affected by the wake-up;
the SOSC oscillator continues to run (see
IDLEN and SCS bits are not affected by the wake-up;
the SOSC oscillator continues to run (see
).
FIGURE 3-6:
TRANSITION TIMING FOR ENTRY TO IDLE MODE
Q3 Q4 Q1 Q2
OSC1
Peripheral
Program
PC
PLL Clock
Q3 Q4
Output
CPU Clock
Q1
Q2 Q3 Q4 Q1 Q2
Clock
Counter
PC + 6
PC + 4
Q1 Q2 Q3 Q4
Wake Event
Note 1: T
OST
= 1024 T
OSC
; T
PLL
= 2 ms (approx). These intervals are not shown to scale.
T
OST
(1)
T
PLL
(1)
OSTS bit set
PC + 2
Note:
The SOSC oscillator should already be
running prior to entering SEC_IDLE
mode. At least one of the secondary oscil-
lator enable bits (SOSCGO, T1SOSCEN,
T3SOSCEN or T5SOSCEN) must be set
when the SLEEP instruction is executed.
Otherwise, the main system clock will con-
tinue to operate in the previously selected
mode and the corresponding IDLE mode
will be entered (i.e., PRI_IDLE or
RC_IDLE).
running prior to entering SEC_IDLE
mode. At least one of the secondary oscil-
lator enable bits (SOSCGO, T1SOSCEN,
T3SOSCEN or T5SOSCEN) must be set
when the SLEEP instruction is executed.
Otherwise, the main system clock will con-
tinue to operate in the previously selected
mode and the corresponding IDLE mode
will be entered (i.e., PRI_IDLE or
RC_IDLE).
Q1
Peripheral
Program
PC
PC + 2
OSC1
Q3
Q4
Q1
CPU Clock
Clock
Counter
Q2