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Chapter 6 Parallel Input/Output Control
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor
103
6.5.4.5
Port D Drive Strength Selection Register (PTDDS)
6.5.4.6
Port D Interrupt Status and Control Register (PTDSC)
7
6
5
4
3
2
1
0
R
PTDDS7
PTDDS6
PTDDS5
PTDDS4
PTDDS3
PTDDS2
PTDDS1
PTDDS0
W
Reset:
0
0
0
0
0
0
0
0
Figure 6-28. Drive Strength Selection for Port D Register (PTDDS)
Table 6-26. PTDDS Register Field Descriptions
Field
Description
7:0
PTDDS[7:0]
Output Drive Strength Selection for Port D Bits — Each of these control bits selects between low and high
output drive for the associated PTD pin. For port D pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port D bit n.
1 High output drive strength selected for port D bit n.
7
6
5
4
3
2
1
0
R
0
0
0
0
PTDIF
0
PTDIE
PTDMOD
W
PTDACK
Reset:
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-29. Port D Interrupt Status and Control Register (PTDSC)
Table 6-27. PTDSC Register Field Descriptions
Field
Description
3
PTDIF
Port D Interrupt Flag — PTDIF indicates when a port D interrupt is detected. Writes have no effect on PTDIF.
0 No port D interrupt detected.
1 Port D interrupt detected.
2
PTDACK
Port D Interrupt Acknowledge — Writing a 1 to PTDACK is part of the flag clearing mechanism. PTDACK
always reads as 0.
1
PTDIE
Port D Interrupt Enable — PTDIE determines whether a port D interrupt is requested.
0 Port D interrupt request not enabled.
1 Port D interrupt request enabled.
0
PTDMOD
Port A Detection Mode — PTDMOD (along with the PTDES bits) controls the detection mode of the port D
interrupt pins.
0 Port D pins detect edges only.
1 Port D pins detect both edges and levels.