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DEMO9S08DZ60
Chapter 10 Analog-to-Digital Converter (S08ADC12V1)
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor
193
10.5
Initialization Information
This section gives an example that provides some basic direction on how to initialize and configure the
ADC module. You can configure the module for 8-, 10-, or 12-bit resolution, single or continuous
conversion, and a polled or interrupt approach, among many other options. Refer to
ADC module. You can configure the module for 8-, 10-, or 12-bit resolution, single or continuous
conversion, and a polled or interrupt approach, among many other options. Refer to
,
, and
NOTE
Hexadecimal values designated by a preceding 0x, binary values designated
by a preceding %, and decimal values have no preceding character.
by a preceding %, and decimal values have no preceding character.
10.5.1
ADC Module Initialization Example
10.5.1.1
Initialization Sequence
Before the ADC module can be used to complete conversions, an initialization procedure must be
performed. A typical sequence is as follows:
performed. A typical sequence is as follows:
1. Update the configuration register (ADCCFG) to select the input clock source and the divide ratio
used to generate the internal clock, ADCK. This register is also used for selecting sample time and
low-power configuration.
low-power configuration.
2. Update status and control register 2 (ADCSC2) to select the conversion trigger (hardware or
software) and compare function options, if enabled.
3. Update status and control register 1 (ADCSC1) to select whether conversions will be continuous
or completed only once, and to enable or disable conversion complete interrupts. The input channel
on which conversions will be performed is also selected here.
on which conversions will be performed is also selected here.
10.5.1.2
Pseudo-Code Example
In this example, the ADC module is set up with interrupts enabled to perform a single 10-bit conversion
at low power with a long sample time on input channel 1, where the internal ADCK clock is derived from
the bus clock divided by 1.
at low power with a long sample time on input channel 1, where the internal ADCK clock is derived from
the bus clock divided by 1.
ADCCFG = 0x98 (%10011000)
Bit 7
ADLPC
1
Configures for low power (lowers maximum clock speed)
Bit 6:5
ADIV
00
Sets the ADCK to the input clock
÷
1
Bit 4
ADLSMP
1
Configures for long sample time
Bit 3:2
MODE
10
Sets mode at 10-bit conversions
Bit 1:0
ADICLK
00
Selects bus clock as input clock source
ADCSC2 = 0x00 (%00000000)
Bit 7
ADACT
0
Flag indicates if a conversion is in progress
Bit 6
ADTRG
0
Software trigger selected
Bit 5
ACFE
0
Compare function disabled
Bit 4
ACFGT
0
Not used in this example
Bit 3:2
00
Reserved, always reads zero
Bit 1:0
00
Reserved for Freescale’s internal use; always write zero