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DEMO9S08DZ60
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor
229
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time
quanta (Tq) clock cycles per bit (as shown in
quanta (Tq) clock cycles per bit (as shown in
and
Eqn. 12-1
12.3.4.1
MSCAN Receiver Flag Register (CANRFLG)
A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition
which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the
CANRIER register.
which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the
CANRIER register.
Table 12-7. Time Segment 2 Values
TSEG22
TSEG21
TSEG20
Time Segment 2
0
0
0
1 Tq clock cycle
1
1
This setting is not valid. Please refer to
for valid settings.
0
0
1
2 Tq clock cycles
:
:
:
:
1
1
0
7 Tq clock cycles
1
1
1
8 Tq clock cycles
Table 12-8. Time Segment 1 Values
TSEG13
TSEG12
TSEG11
TSEG10
Time segment 1
0
0
0
0
1 Tq clock cycle
1
1
This setting is not valid. Please refer to
for valid settings.
0
0
0
1
2 Tq clock cycles
1
0
0
1
0
3 Tq clock cycles
1
0
0
1
1
4 Tq clock cycles
:
:
:
:
:
1
1
1
0
15 Tq clock cycles
1
1
1
1
16 Tq clock cycles
7
6
5
4
3
2
1
0
R
WUPIF
CSCIF
RSTAT1
RSTAT0
TSTAT1
TSTAT0
OVRIF
RXF
W
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-8. MSCAN Receiver Flag Register (CANRFLG)
Bit Time
Prescaler value
(
)
f
CANCLK
------------------------------------------------------
1
TimeSegment1
TimeSegment2
+
+
(
)
•
=