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DEMO9S08DZ60
Chapter 13 Serial Peripheral Interface (S08SPIV3)
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor
277
Figure 13-3. SPI Module Block Diagram
13.1.3
SPI Baud Rate Generation
As shown in
, the clock source for the SPI baud rate generator is the bus clock. The three
prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate
select bits (SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256
to get the internal SPI master mode bit-rate clock.
select bits (SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256
to get the internal SPI master mode bit-rate clock.
SPI SHIFT REGISTER
SHIFT
CLOCK
SHIFT
DIRECTION
DIRECTION
Rx BUFFER
FULL
Tx BUFFER
EMPTY
SHIFT
OUT
OUT
SHIFT
IN
ENABLE
SPI SYSTEM
CLOCK
LOGIC
CLOCK GENERATOR
BUS RATE
CLOCK
MASTER/SLAVE
MODE SELECT
MODE FAULT
DETECTION
MASTER CLOCK
SLAVE CLOCK
SPI
INTERRUPT
REQUEST
INTERRUPT
REQUEST
PIN CONTROL
M
S
MASTER/
SLAVE
SLAVE
MOSI
(MOMI)
(MOMI)
MISO
(SISO)
(SISO)
SPSCK
SS
M
S
S
M
SPIBR
Tx BUFFER (WRITE SPID)
Rx BUFFER (READ SPID)