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DEMO9S08DZ60
Appendix A Electrical Characteristics
MC9S08DZ60 Series Data Sheet, Rev. 4
386
Freescale Semiconductor
A.12.4
SPI
through
Table A-16. SPI Electrical Characteristic
Num
1
1
Refer to
through
C
Rating
2
2
All timing is shown with respect to 20% V
DD
and 70% V
DD
, unless noted; 100 pF load on all SPI
pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output
pins.
pins.
Symbol
Min
Max
Unit
1
D
Cycle time
Master
Slave
t
SCK
t
SCK
2
4
4
2048
—
t
cyc
t
cyc
2
D
Enable lead time
Master
Slave
t
Lead
t
Lead
—
1/2
1/2
—
t
SCK
t
SCK
3
D
Enable lag time
Master
Slave
t
Lag
t
Lag
—
1/2
1/2
—
t
SCK
t
SCK
4
D
Clock (SPSCK) high time
Master and Slave
t
SCKH
(1/2 t
SCK
)– 25
—
ns
5
D
Clock (SPSCK) low time
Master and Slave
t
SCKL
(1/2 t
SCK
) – 25
—
ns
6
D
Data setup time (inputs)
Master
Slave
t
SI(M)
t
SI(S)
30
30
30
—
—
—
ns
ns
ns
7
D
Data hold time (inputs)
Master
Slave
t
HI(M)
t
HI(S)
30
30
30
—
—
—
ns
ns
ns
8
D
Access time, slave
3
3
Time to data active from high-impedance state.
t
A
0
40
ns
9
D
Disable time, slave
4
4
Hold time to high-impedance state.
t
dis
—
40
ns
10
D
Data setup time (outputs)
Master
Slave
t
SO
t
SO
25
25
25
—
—
—
ns
ns
ns
11
D
Data hold time (outputs)
Master
Slave
t
HO
t
HO
–10
–10
–10
—
—
—
ns
ns
ns
12
D
Operating frequency
5
Master
Slave
5
Maximum baud rate must be limited to 5 MHz due to pad input characteristics.
f
op
f
op
f
Bus
/2048
dc
5
f
Bus
/4
MHz