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Appendix B Timer Pulse-Width Modulator (TPMV2)
MC9S08DZ60 Series Data Sheet, Rev. 4
398
Freescale Semiconductor
If the associated port pin is not stable for at least two bus clock cycles before changing to input capture
mode, it is possible to get an unexpected indication of an edge trigger. Typically, a program would clear
status flags after changing channel configuration bits and before enabling channel interrupts or using the
status flags to avoid any unexpected behavior.
B.2.5
Timer Channel Value Registers (TPMxCnVH:TPMxCnVL)
These read/write registers contain the captured TPM counter value of the input capture function or the
output compare value for the output compare or PWM functions. The channel value registers are cleared
by reset.
Table B-5. Mode, Edge, and Level Selection
 CPWMS
 MSnB:MSnA
 ELSnB:ELSnA
 Mode
 Configuration
X
XX
00
Pin not used for TPM channel; use as an external clock for the TPM or
revert to general-purpose I/O
0
00
01
Input capture
Capture on rising edge only
10
Capture on falling edge only
11
Capture on rising or falling edge
01
00
Output
compare
Software compare only
01
Toggle output on compare
10
Clear output on compare
11
Set output on compare
1X
10
Edge-aligned
PWM
High-true pulses (clear output on compare)
X1
Low-true pulses (set output on compare)
1
XX
10
Center-aligned
PWM
High-true pulses (clear output on compare-up)
X1
Low-true pulses (set output on compare-up)
7
6
5
4
3
2
1
0
R
Bit 15
14
13
12
11
10
9
Bit 8
W
Reset
0
0
0
0
0
0
0
0
Figure B-8. Timer Channel Value Register High (TPMxCnVH)
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reset
0
0
0
0
0
0
0
0
Figure B-9. Timer Channel Value Register Low (TPMxCnVL)